Yue Li

US Patent:

20220394240, Dec 8, 2022

Filed:

Jun 1, 2022

Appl. No.:

17/829892

Inventors:

- Grand Cayman, KY
Li Zhang - San Diego CA, US
Yue Li - San Diego CA, US
Kai Zhang - San Diego CA, US

International Classification:

H04N 19/105
H04N 19/107
H04N 19/137
H04N 19/176

Abstract:

A mechanism for processing video data is disclosed. A determination is made to apply an end-to-end neural network-based video codec to a current video unit of a video. The end-to-end neural network-based video codec comprises a spatial-temporal adaptive compression (STAC) component including a frame extrapolative compression (FEC) branch and an image compression branch. A conversion is performed between the current video unit and a bitstream of the video via the end-to-end neural network-based video codec.

US Patent:

20230102167, Mar 30, 2023

Filed:

Sep 24, 2021

Appl. No.:

17/484475

Inventors:

- San Diego CA, US
Durodami Lisk - San Diego CA, US
Yue Li - San Diego CA, US

International Classification:

H01L 25/10
H01L 23/498
H01L 23/00
H01L 25/00

Abstract:

Multiple (multi-) die integrated circuit (IC) packages for supporting higher connection density, and related fabrication methods. The multi-die IC package includes split dies that provided in respective die packages that are stacked on top of each other to conserve package area. To support signal routing, including through-package signal routing that extends through the die package, each die package includes vertical interconnects disposed adjacent to their respective dies and coupled to a respective package substrate (and interposer substrate if provided) in the package substrate. In this manner, as an example, through-silicon-vias (TSVs) are not required to be fabricated in the multi-die IC package that extend through the dies themselves to provide signal routing between the respective die packages. In another example, space created between adjacent interposer substrates of stacked die packages, as stood off from each other through the interconnect bumps, provides an area for heat dissipation.

US Patent:

20210125951, Apr 29, 2021

Filed:

Oct 28, 2019

Appl. No.:

16/665883

Inventors:

- San Diego CA, US
Yue LI - San Diego CA, US
Yangyang SUN - San Diego CA, US

International Classification:

H01L 23/00

Abstract:

An integrated device that includes a substrate, an interconnect portion and an interconnect structure. The interconnect portion is located over the substrate. The interconnect portion includes a plurality of interconnects and at least one dielectric layer. The interconnect structure is located over the interconnect portion. The interconnect structure includes an inner interconnect, a dielectric layer coupled to the inner interconnect, and an outer conductive layer coupled to the dielectric layer. The outer conductive layer is configured to operate as a shield for the inner interconnect.

US Patent:

20200176417, Jun 4, 2020

Filed:

Dec 4, 2018

Appl. No.:

16/209723

Inventors:

- San Diego CA, US
Yue LI - San Diego CA, US
Kuiwon KANG - San Diego CA, US
Soumyadipta BASU - San Diego CA, US
Joan Rey Villarba BUOT - Escondido CA, US

International Classification:

H01L 25/065
H01L 23/538
H01L 23/64
H01L 23/00
H05K 1/18

Abstract:

The present disclosure generally relates to an integrated circuit having a stacked embedded passive substrate (EPS) structure formed therein. In particular, a substrate may have a cavity formed therein and the stacked EPS structure may include multiple passive components formed in the cavity to provide separate electrical paths for decoupling of the integrated circuit. Furthermore, the multiple passive components may each have two respective terminals such that the multiple passive components may support different voltage domains. Among other things, compared to conventional die-side and/or land-side passive components, the stacked EPS structure may advantageously reduce a z-axis height of the integrated circuit, reduce manufacturing costs, improve performance due to shorter electrical paths, and improve design routing through x-axis and y-axis space savings.

US Patent:

20190043817, Feb 7, 2019

Filed:

Sep 14, 2018

Appl. No.:

16/132315

Inventors:

- San Diego CA, US
Haiyong XU - San Diego CA, US
Ruey Kae ZANG - Jamesville NY, US
Yue LI - San Diego CA, US
Xiaonan ZHANG - San Diego CA, US
Christine HAU-RIEGE - Fremont CA, US

International Classification:

H01L 23/00

Abstract:

The present disclosure provides packages and methods for fabricating packages. A package may comprise a wafer-level package (WLP) layer comprising a WLP contact and a component within the WLP layer associated with a component depth. A conductive pillar is disposed on the WLP contact and comprises an opposite surface that forms an array pad. The package further comprises a mold over the WLP layer and at least partially surrounding the conductive pillar, wherein the mold compound and the array pad form a substantially planar land grid array (LGA) contact surface that is configured to couple the package to a land grid array. The LGA contact surface has a height that is equal to a selected LGA component height, and the selected LGA component height is equal to a difference between a keepout distance associated with a characteristic of the component within the WLP layer and the component depth.

US Patent:

20180053740, Feb 22, 2018

Filed:

Aug 22, 2016

Appl. No.:

15/243923

Inventors:

- San Diego CA, US
Haiyong XU - San Diego CA, US
Ruey Kae ZANG - San Diego CA, US
Yue LI - San Diego CA, US
Xiaonan ZHANG - San Diego CA, US
Christine HAU-RIEGE - Fremont CA, US

International Classification:

H01L 23/00

Abstract:

The present disclosure provides packages and methods for fabricating packages. A package may comprise a wafer-level package (WLP) layer comprising first and second WLP contacts and first and second conductive pillars disposed on the first and second WLP contacts. Each conductive pillar may comprise a surface opposite the WLP contact that forms an array pad. The array pads may have different sizes. The package may further comprise a mold over the WLP layer and at least partially surrounding the conductive pillars, wherein the mold compound and the first array pads form a substantially planar LGA contact surface that is configured to couple the package to a land grid array.

US Patent:

20170373032, Dec 28, 2017

Filed:

Jun 24, 2016

Appl. No.:

15/192825

Inventors:

- San Diego CA, US
Ruey Kae ZANG - San Diego CA, US
Lizabeth Ann KESER - San Diego CA, US
Reynante Tamunan ALVARADO - San Diego CA, US
Haiyong XU - San Diego CA, US
Yue LI - San Diego CA, US
Steve BEZUK - Poway CA, US

International Classification:

H01L 23/00
H01L 23/31
H01L 23/498

Abstract:

Disclosed is a fan-out wafer level packaging (FOWLP) apparatus includes a semiconductor die having at least one input/output (I/O) connection, a first plurality of package balls having a first package ball layout, a first conductive layer forming a first redistribution layer (RDL) and configured to electrically couple to the first plurality of package balls, and a second conductive layer forming a second RDL and including at least one conductive pillar configured to electrically couple the at least one I/O connection of the semiconductor die to the first conductive layer, wherein the second conductive layer enables the semiconductor die to be electrically coupled to a second plurality of package balls having a second package ball layout without a change in position of the at least one I/O connection of the semiconductor die.

US Patent:

20170005160, Jan 5, 2017

Filed:

Dec 17, 2015

Appl. No.:

14/973479

Inventors:

- San Diego CA, US
Yue LI - San Diego CA, US
Ratibor RADOJCIC - San Diego CA, US

International Classification:

H01L 49/02
H01L 23/532
H01L 23/522

Abstract:

Copper (Cu) grain boundaries can move during a thermal cycle resulting in the Cu grain position being offset. Such Cu pumping can disturb the surface of a bottom metal, and can physically break a dielectric of a metal-insulator-metal (MIM) capacitor. By capping the bottom metal with an anchoring cap, Cu pumping is reduced or eliminated.