Yun Han Chiu

US Patent:

61778389, Jan 23, 2001

Filed:

Nov 25, 1998

Appl. No.:

9/200180

Inventors:

Yun Chiu - Fremont CA

Assignee:

PixArt Technology, Inc. - Fremont CA

International Classification:

H03F 345
H03F 122

US Classification:

330253

Abstract:

A gain enhanced cascoded CMOS amplifier includes: a cascading transistor having its source connected to a folding point node, its drain connected to a first amplifier output terminal, and a gate, the folding point node being coupled to a first power supply terminal; a gain enhancing circuit having a negative input terminal coupled to the first folding point node, a positive input terminal responsive to a first reference voltage source, and an output terminal coupled to the gate of the first cascoding transistor; a first output coupling circuit coupling the first amplifier output terminal to a second power supply terminal; a first input transistor having a gate responsive to a first input voltage, a source, and a drain, the first input transistor having particular physical dimensions; and a first pole-isolating transistor having a drain connected to the first folding point node, a source connected to the drain of the first input transistor, and a gate responsive to an isolation bias voltage, the first pole isolating transistor having smaller physical dimensions than the particular physical dimensions of the first input transistor, wherein capacitive loading at the first folding point node is minimized to provide optimal settling behavior and stability in operation of the amplifier.