Yun O Lee

US Patent:

20200243707, Jul 30, 2020

Filed:

Apr 13, 2020

Appl. No.:

16/847038

Inventors:

- Armonk NY, US
Yun Seog Lee - White Plains NY, US
Saurabh Singh - Yonkers NY, US
Teodor K. Todorov - Yorktown Heights NY, US

International Classification:

H01L 31/18
H01L 31/0749
H01L 31/0224
H01L 31/0468
H01L 31/0272

Abstract:

Semitransparent chalcogen solar cells and techniques for fabrication thereof are provided. In one aspect, a method of forming a solar cell includes: forming a first transparent contact on a substrate; depositing an n-type layer on the first transparent contact; depositing a p-type chalcogen absorber layer on the n-type layer, wherein a p-n junction is formed between the p-type chalcogen absorber layer and the n-type layer; depositing a protective interlayer onto the p-type chalcogen absorber layer, wherein the protective interlayer fully covers the p-type chalcogen absorber layer; and forming a second transparent contact on the interlayer, wherein the interlayer being disposed between the p-type chalcogen absorber layer and the second transparent contact serves to protect the p-n junction during the forming of the second transparent contact. Solar cells and other methods for formation thereof are also provided.

US Patent:

20200243784, Jul 30, 2020

Filed:

Apr 13, 2020

Appl. No.:

16/846971

Inventors:

- Armonk NY, US
Yun Seog Lee - White Plains NY, US
Saurabh Singh - Yonkers NY, US
Teodor K. Todorov - Yorktown Heights NY, US

International Classification:

H01L 51/42
H01L 31/0272

Abstract:

Selenium-fullerene heterojunction solar cells and techniques for fabrication thereof are provided. In one aspect, a method of forming a solar cell includes: forming a front contact on a substrate; depositing an n-type semiconducting layer on the front contact, wherein the n-type semiconducting layer comprises a fullerene or fullerene derivative; forming a p-type chalcogen absorber layer on the n-type semiconducting layer; depositing a high workfunction material onto the p-type chalcogen absorber layer, wherein the high workfunction material has a workfunction of greater than about 5.2 electron volts; and forming a back contact on the high workfunction material. Solar cells and other methods for formation thereof are also provided.

US Patent:

20190051930, Feb 14, 2019

Filed:

Aug 11, 2017

Appl. No.:

15/675296

Inventors:

- Armonk NY, US
Yun Seog Lee - White Plains NY, US
Devendra K. Sadana - Pleasantville NY, US

International Classification:

H01M 10/0562
H01M 10/0525
H01M 10/04
H01M 4/131
H01M 4/525
H01M 4/1391
H01M 10/0585
H01M 4/04

Abstract:

A solid-state lithium-based battery having fast charging and recharging speeds (above 3 C) is provided by including a nitrogen-enriched lithiated cathode material surface layer between the lithiated cathode material layer and the lithium-based solid-state electrolyte layer. The nitrogen-enriched lithiated cathode material surface layer can be formed by introducing nitrogen into a lithiated cathode material. The nitrogen can be introduced during the final stage of a deposition process or by utilizing a different process, such as, for example, thermal nitridation, than a deposition process.

US Patent:

20180309075, Oct 25, 2018

Filed:

Apr 25, 2017

Appl. No.:

15/496740

Inventors:

- Armonk NY, US
Guy M. Cohen - Ossining NY, US
Talia S. Gershon - White Plains NY, US
Yun Seog Lee - White Plains NY, US
Ning Li - White Plains NY, US
Devendra K. Sadana - Pleasantville NY, US

International Classification:

H01L 51/10
H01L 51/05
H01L 51/00
G11C 13/00

Abstract:

Memristive devices based on tunable Schottky barrier are provided. In one aspect, a method of forming a memristive device includes: forming a semiconductor layer on a bottom metal electrode, wherein the semiconductor layer has workfunction-modifying molecules embedded therein; and forming a top metal electrode on the semiconductor layer, wherein the top metal electrode forms a Schottky junction with the semiconductor layer, and wherein the workfunction-modifying molecules are configured to alter a workfunction of the top metal electrode. A memristive device and a method for operating a memristive device are also provided.

US Patent:

20180294159, Oct 11, 2018

Filed:

Apr 5, 2017

Appl. No.:

15/480232

Inventors:

- Armonk NY, US
Yun Seog LEE - White Plains NY, US
Devendra K. SADANA - Pleasantville NY, US

International Classification:

H01L 21/28
H01L 21/3213
H01L 21/285
H01L 21/311

Abstract:

Embodiments herein describe techniques for forming sidewalls on vertical structures on a semiconductor substrate. In one embodiment, the semiconductor substrate includes a first layer (e.g., a conductive layer such as an electrode) on which a second layer (e.g., an insulator) is disposed. An undercut etch is performed which selectively etches the sides of the material in the first layer but not the material in the second layer. A conformal deposition process is used to deposit the material of the sidewall into the undercut regions. Further etches can be performed to shape the sidewalls disposed on the sides of the material in the first layer.

US Patent:

20180294163, Oct 11, 2018

Filed:

Apr 5, 2017

Appl. No.:

15/480224

Inventors:

- Armonk NY, US
Yun Seog Lee - White Plains NY, US
Devendra K Sadana - Pleasantville NY, US

International Classification:

H01L 21/3065
H01L 21/308
H01L 21/02

Abstract:

Embodiments herein describe techniques for forming a zinc oxide mask used when performing RIE. In one embodiment, the zinc oxide mask is near-amorphous which means the zinc oxide has a grain size that is less than 50 nanometers. In contrast, metal masks such as aluminum, chromium, and titanium have a less robustness to ME process. When performing RIE, the edges of these ME masks can form pits or holes which harm the features of the underlying substrate. However, a near-amorphous zinc oxide ME mask is less susceptible to pitting, and thus, can improve the geometry of the etched features.

US Patent:

20180294526, Oct 11, 2018

Filed:

Apr 6, 2017

Appl. No.:

15/481042

Inventors:

- Armonk NY, US
Yun Seog Lee - White Plains NY, US
Ning Li - White Plains NY, US
Devendra K. Sadana - Pleasantville NY, US

International Classification:

H01M 10/0585
H01M 2/34
H01M 10/0525
H01M 2/26
H01M 4/131
H01M 2/20

Abstract:

Solid-state battery structures, particularly solid-state lithium-based battery structures, which are fast charging and have a high capacity are provided. Notably, fast charging, high capacity solid-state battery structures are provided that include a plurality of solid-state-thin-film batteries that are stacked one atop the other, or that include an array of interconnected solid-state thin-film batteries, or that contain a solid-state thin-film battery located on physically exposed surfaces of fin structures.

US Patent:

20180294527, Oct 11, 2018

Filed:

Nov 20, 2017

Appl. No.:

15/818286

Inventors:

- Armonk NY, US
Yun Seog Lee - White Plains NY, US
Ning Li - White Plains NY, US
Devendra K. Sadana - Pleasantville NY, US

International Classification:

H01M 10/0585
H01M 2/20
H01M 4/131
H01M 10/0525
H01M 2/34
H01M 2/26

Abstract:

Solid-state battery structures, particularly solid-state lithium-based battery structures, which are fast charging and have a high capacity are provided. Notably, fast charging, high capacity solid-state battery structures are provided that include a plurality of solid-state-thin-film batteries that are stacked one atop the other, or that include an array of interconnected solid-state thin-film batteries, or that contain a solid-state thin-film battery located on physically exposed surfaces of fin structures.