Arthur Lin - San Jose CA Kui K. Yau - Saratoga CA Yuncheng F. Yu - Palo Alto CA
Assignee:
Sun Microsystems, Inc. - Palo Alto CA
International Classification:
G06F 1750
US Classification:
39550003
Abstract:
In a control block design methodology, a control block is designed, synthesized, and laid out. The control block includes one or more storage devices, such as flops. The flops include a header which buffers signals common to the flops and a storage cell for storing data. A flop grouping tool is used to merge flops having the same type of header into a flop having storage equivalent to the merged flops but using a single header. Multiple instances of the header may be deleted from the control block.
Automated Scan Insertion Flow For Control Block Design
Sridhar Narayanan - Sunnyvale CA Yuncheng F. Yu - Palo Alto CA Arthur Lin - San Jose CA Hongyu Li - Hayward CA
Assignee:
Sun Microsystems, Inc. - Palo Alto CA
International Classification:
G01R 3128
US Classification:
714726
Abstract:
In a control block design methodology, control block design proceeds without the inclusion of scan functionality until the functional design specifications are met. After meeting the functional design specifications, a scan insertion tool is executed to automatically insert scan functionality. The insertion is performed in such a manner that the functional cells within the control block are not perturbed. Therefore, functional timing may be minimally affected, if at all. In one embodiment, a scan enable buffer is inserted at the end of each row in the control block. Flops (or other scannable storage devices) within the row are connected to the scan enable line provided by the scan enable buffer within the row. Additionally, flops are connected into a scan chain on a row-by-row basis, minimizing the length of the wires connecting the scan chain. If a particular scan chain wire exceeds a length which will meet scan timing requirements, a scan chain buffer can be inserted as well (e. g.
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