Sukanta Banerjee - North Brunswick NJ, US Michael Seul - Fanwood NJ, US Alice Li - Ithaca NY, US Kairali Podual - North Brunswick NJ, US Chiu Chau - Edison NJ, US Zhi Li - Irvington NY, US
International Classification:
C12Q001/68 G01N033/53 G01N033/553
US Classification:
435006000, 435007100, 436526000
Abstract:
The present invention provides a method for the generation of novel libraries of encoded magnetic particles from sub-libraries of by the generation of novel sub- libraries of magnetic nanoparticles and encoded particles. The sub-libraries are functionalized on demand are useful in the formation of arrays. The present invention is especially useful for performing multiplexed (parallel) assays for qualitative and/or quantitative analysis of binding interactions of a number of analyte molecules in a sample.
System And Method For Predicting A Fault In A Real-Time Transport Protocol Packet Stream
MOSHIUR RAHMAN - MARLBORO NJ, US ZHI LI - MARTINEZ CA, US
Assignee:
AT&T KNOWLEDGE VENTURES, L.P. - RENO NV
International Classification:
H04L 12/56
US Classification:
370242, 370390
Abstract:
A system that incorporates teachings of the present disclosure may include, for example, a monitoring system having a controller element to predict a fault in a video stream of real-time transport protocol (RTP) packets according to gaps in sequence numbers of said RTP packets. Other embodiments are disclosed.
Method And System For Detecting A Fault Condition Based On Failed Igmp Join Attempts
Moshiur Rahman - Marlboro NJ, US Zhi Li - Martinez CA, US
Assignee:
AT&T KNOWLEDGE VENTURES, LP - Reno NV
International Classification:
G06F 11/30
US Classification:
370242
Abstract:
A fault condition is detected based on determining that a number of failed Internet Group Management Protocol (IGMP) join attempts from at least one end device is greater than or equal to a threshold.
System And Method To Troubleshoot A Set Top Box Device
Paritosh Bajpay - Edison NJ, US Zhi Li - San Ramon CA, US David Lu - Morganville NJ, US Balaji Puli - San Ramon CA, US Raghvendra Savoor - Walnut Creek CA, US Anthony Srdar - Dawsonville GA, US
Assignee:
AT&T INTELLECTUAL PROPERTY I, L.P. - Reno NV
International Classification:
H04H 60/32
US Classification:
725 16
Abstract:
A computer-implemented method includes receiving, at a monitoring center of a media distribution network, from a set top box device associated with a customer account, first error data indicating occurrence of a first error at the set top box device at a first time. The set top box device is at least partially functional after occurrence of the first error. The computer-implemented method includes receiving, at the monitoring center, second error data indicating occurrence of a second error at the set top box device at a second time. The set top box device is at least partially functional after occurrence of the second error. The computer-implemented method includes determining an elapsed time between the first time and the second time. The computer-implemented method includes automatically generating a trouble ticket indicating failure of the set top box device when the elapsed time satisfies a first threshold.
Smoothies Technology, Inc New York, NY Sep 2014 to Feb 2015 Software ConsultantSmart Team Global LLC
Sep 2013 to Sep 2014 Technical ConsultantUniversity of Detroit Mercy School of Dentistry
Sep 2012 to Aug 2013 Software Researcher
Education:
University of Detroit Mercy May 2013 Master of Science in Software EngineeringChengdu University of Information Technology Jun 2011 Bachelor of Science in Geography Information System
New Jersey Institute of Technology Newark, NJ 2009 to 2013 Ph.D in Electrical Engineering, VLSI and Solid State DeviceNew Jersey Institute of Technology Newark, NJ 2007 to 2008 M. S. in Electrical & Computer EngineeringBeijing Institute of Technology 1984 to 1988 BSc in Electrical Engineering
Skills:
4 Years of X-ray semiconductor detector ASIC and board level design&test experience in Dr. Siddons Detector development group, Brookhaven National Lab. Specialized in the area of VLSI design, skilled at both analog and digital circuit ASIC design with Cadence virtuoso schematic, layout and simulation, Mentor Graphic schematic capture, IC station and HSPICE simulation; and VHDL/Verilog programming, Modsim simulation and Xilinx/Altera FPGA development. Specialized in the board level circuit design&test by using the Mentor Graphic board station and PADS for circuit and layout, PSPICE for simulation, various test instruments for design verification test and debug. Many years of circuit board level design in Lucent Technologies.
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