Zhi G Zhang

US Patent:

20130152103, Jun 13, 2013

Filed:

Dec 7, 2012

Appl. No.:

13/707621

Inventors:

International Business Machines Corporation - Armonk NY, US
William P. LEPERA - Poughkeepsie NY, US
HanHong XUE - Wappingers Falls NY, US
Zhi ZHANG - Poughkeepsie NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9/52

US Classification:

718104

Abstract:

A job may be divided into multiple tasks that may execute in parallel on one or more compute nodes. The tasks executing on the same compute node may be coordinated using barrier synchronization. However, to perform barrier synchronization, the tasks use (or attach) to a barrier synchronization register which establishes a common checkpoint for each of the tasks. A leader task may use a shared memory region to publish to follower tasks the location of the barrier synchronization register—i.e., a barrier synchronization register ID. The follower tasks may then monitor the shared memory to determine the barrier synchronization register ID. The leader task may also use a count to ensure all the tasks attach to the BSR. This advantageously avoids any task-to-task communication which may reduce overhead and improve performance.