Zimri C Putney

US Patent:

43262120, Apr 20, 1982

Filed:

Aug 27, 1979

Appl. No.:

6/069645

Inventors:

David L. Bergeron - Manassas VA
Zimri C. Putney - Fairfax VA
Geoffrey B. Stephens - Catlett VA

Assignee:

IBM Corporation - Armonk NY

International Classification:

H01L 2704
H03K 19081

US Classification:

357 46

Abstract:

An improved I. sup. 2 L structure and process are disclosed which reduces the minority carrier charge storage, increases the emitter injection efficiency and reduces the emitter diffusion capacitance in the upward injecting vertical NPN transistor and reduces the minority carrier charge storage and increases the collector efficiency in the lateral PNP transistor. This is accomplished by ion-implanting a p-type region in the epitaxial layer, through an insulating layer on the surface having an emitter window over the vertical NPN transistor, so that its concentration contour peak follows the contour of the insulating layer so as to be closer to the subemitter in the intrinsic base region than in the extrinsic base region of the vertical transistor, thereby imposing a concentration gradient induced electric field in the intrinsic base region which will aid in the movement of the minority carrier charges from the buried emitter into the intrinsic base region of the vertical transistor while at the same time reducing the tendency of the minority carriers to stay in the region of the epitaxial layer between the subemitter and the base in the vertical NPN and between the buried N region and the collector region of the lateral PNP.

US Patent:

41101260, Aug 29, 1978

Filed:

Aug 31, 1977

Appl. No.:

5/829302

Inventors:

David L. Bergeron - Manassas VA
Zimri C. Putney - Fairfax VA
Geoffrey B. Stephens - Catlett VA

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21265

US Classification:

148 15

Abstract:

An improved merged transistor logic (I. sup. 2 L) process is disclosed which provides a practical technique for forming micron to sub-micron window size devices. In a single step, the process forms all of the contact and guard ring windows in the passivation layer and then by use of selective blocking of various combinations of these windows, the various ion-implanted regions of the devices are formed with a minimum number of hot processing steps. A second embodiment of the method forms a double diffused lateral PNP device having an asymmetrically placed emitter within the base so as to enhance the injection efficiency in the vicinity of the collector. A micron to sub-micron window for the formation of all contacts and guard ring permits a merged transistor logic structure to be formed having a reduced upward NPN collector-base capacitance, lower PNP emitter-base diffusion capacitance, a lower PNP base series resistance, and an increased probability of avoiding collector-emitter pipe defects. The formation of all the windows in the passivation layer and the use of selective photoresist blocking to define the various ion-implanted regions in the device permit the practical formation of a minimum size (self-aligned contact to guard ring) MTL device with a minimum number of critical mask and hot processing steps. The advantages also apply to downward NPN and individual PNP devices.