Aaron David Lowe

US Patent:

20220352324, Nov 3, 2022

Filed:

Jul 18, 2022

Appl. No.:

17/867579

Inventors:

- Boise ID, US
Aaron Michael Lowe - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 21/28
H01L 27/11502
H01L 27/108
G11C 11/22
G11C 5/06
H01L 29/78
H01L 27/06

Abstract:

Some embodiments include an integrated transistor having an active region comprising semiconductor material. The active region includes a first source/drain region, a second source/drain region and a channel region between the first and second source/drain regions. A conductive gating structure is operatively proximate the channel region and comprises molybdenum. The integrated transistor may be incorporated into integrated memory, such as, for example, DRAM, FeFET memory, etc. Some embodiments include methods of forming integrated assemblies and devices, such as, for example, integrated transistors, integrated memory, etc.

US Patent:

20210366525, Nov 25, 2021

Filed:

Aug 9, 2021

Appl. No.:

17/397028

Inventors:

- Boise ID, US
Richard J. Hill - Boise ID, US
Aaron Michael Lowe - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 7/18
H01L 27/11582
H01L 27/11556
H01L 27/11524
H01L 27/1157

Abstract:

A method used in forming a memory array comprises forming digitlines above and electrically couple to memory cells there-below. The digitlines are laterally-spaced relative one another in a vertical cross-section. An upwardly-open void-space is laterally-between immediately-adjacent of the digitlines in the vertical cross-section. Conductive material of the digitlines is covered with masking material that is in and less-than-fills the upwardly-open void-spaces. The masking material is removed from being directly above tops of the digitlines to expose the conductive digitline material and to leave the masking material over sidewalls of the conductive digitline material in the upwardly-open void-spaces. Insulative material is selectively grown from the exposed conductive digitline material relative to the masking material across the upwardly-open void-spaces to form covered void-spaces there-from between the immediately-adjacent digitlines in the vertical cross-section. Structures independent of method are disclosed.

US Patent:

20210257012, Aug 19, 2021

Filed:

Feb 18, 2020

Appl. No.:

16/793263

Inventors:

- Boise ID, US
Richard J. Hill - Boise ID, US
Aaron Michael Lowe - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 7/18
H01L 27/11582
H01L 27/1157
H01L 27/11524
H01L 27/11556

Abstract:

A method used in forming a memory array comprises forming digitlines above and electrically couple to memory cells there-below. The digitlines are laterally-spaced relative one another in a vertical cross-section. An upwardly-open void-space is laterally-between immediately-adjacent of the digitlines in the vertical cross-section. Conductive material of the digitlines is covered with masking material that is in and less-than-fills the upwardly-open void-spaces. The masking material is removed from being directly above tops of the digitlines to expose the conductive digitline material and to leave the masking material over sidewalls of the conductive digitline material in the upwardly-open void-spaces. Insulative material is selectively grown from the exposed conductive digitline material relative to the masking material across the upwardly-open void-spaces to form covered void-spaces there-from between the immediately-adjacent digitlines in the vertical cross-section. Structures independent of method are disclosed.