Aldo G Cometti

US Patent:

RE38045, Mar 25, 2003

Filed:

Jul 7, 2000

Appl. No.:

09/612540

Inventors:

Aldo Giovanni Cometti - San Diego CA
R. Frank OBleness - Del Mar CA

Assignee:

STMicroelectronics, Inc. - Carrollton TX

International Classification:

H03L 706

US Classification:

327156, 327159, 327292

Abstract:

A circuit that compensates for delays induced by clock generation logic and distributed clock drivers in phase lock loop applications is disclosed. The circuit is a phase lock loop (PLL) which contains a clock synchronization circuit that operates to synchronize a transition edge of a signal generated by a frequency divider against a distributed clock signal generated by a clock output driver of the circuit. The synchronization occurs unless the clock synchronization circuit is disabled.

US Patent:

8644099, Feb 4, 2014

Filed:

Jul 8, 2011

Appl. No.:

13/179466

Inventors:

Aldo G. Cometti - San Diego CA, US
Lun Bin Huang - San Diego CA, US
Ashot Melik-Martirosian - San Diego CA, US

Assignee:

STEC, Inc. - Santa Ana CA

International Classification:

G11C 7/00

US Classification:

365201, 36518518, 365226

Abstract:

Disclosed is an apparatus and method for determining a dwell time in a non-volatile memory circuit after a shutdown of the memory circuit. A voltage shift is calculated by comparing a first read level voltage required to read a test block stored before the shutdown and a second read level voltage required to read a second test block stored after the shutdown. A shutdown time is determined from a look up table indexed by the voltage shift and a number of program/erase cycles. The dwell time is calculated as a function of the drive temperature, a clock, and a block time stamp. Once the dwell time is calculated, a controller calculates a new read level voltage based, in part, on the dwell time and provides one or more programming commands representative of the new read level voltage to the memory circuit to read the memory circuit.

US Patent:

20120236656, Sep 20, 2012

Filed:

Mar 30, 2011

Appl. No.:

13/076340

Inventors:

Aldo G. COMETTI - San Diego CA, US

Assignee:

STEC, INC. - Santa Ana CA

International Classification:

G11C 16/06
G11C 16/04

US Classification:

36518522, 36518518

Abstract:

Disclosed is an apparatus and method for determining a read level voltage to apply to a block of memory cells in a non-volatile memory circuit. A prediction value is compared to a prediction indicator to determine whether a new read level voltage to be applied to read the memory cells should be estimated. If a new read level should be estimated the new read level is calculated as a function of an initial read level and a dwell time and a number of program/erase cycles. A controller provides one or more programming commands representative of the new read level voltage to the memory circuit to read the cells.

US Patent:

57774986, Jul 7, 1998

Filed:

Dec 2, 1996

Appl. No.:

8/758962

Inventors:

Aldo Giovanni Cometti - Phoenix AZ
R. Frank O'Bleness - Glendale AZ

Assignee:

SGS-Thomson Microelectronics, Inc. - Carrollton TX

International Classification:

H03L 706

US Classification:

327156

Abstract:

A circuit that compensates for delays induced by clock generation logic and distributed clock drivers in phase lock loop applications is disclosed. The circuit is a phase lock loop (PLL) which contains a clock synchronization circuit that operates to synchronize a transition edge of a signal generated by a frequency divider against a distributed clock signal generated by a clock output driver of the circuit. The synchronization occurs unless the clock synchronization circuit is disabled.

US Patent:

20210319837, Oct 14, 2021

Filed:

Jun 25, 2021

Appl. No.:

17/359352

Inventors:

- San Jose CA, US
Aldo Giovanni COMETTI - San Diego CA, US
Richard Leo GALBRAITH - Rochester MN, US
Jonas Andrew GOODE - Lake Forest CA, US
Niranjay RAVINDRAN - Rochester MN, US
Anthony Dwayne WEATHERS - San Diego CA, US

International Classification:

G11C 16/34
G06F 3/06
G11C 11/56
G11C 29/02
G06F 11/10

Abstract:

Systems and methods for read level tracking and optimization are described. Pages from a wordline of a flash memory device read and the raw page data read from the wordline may be buffered in a first set of buffers. The raw page data for each of the pages may be provided to a decoder for decoding and the decoded page data for each of the pages buffered in a second set of buffers. First bin identifiers may be identified for memory cells of the wordline based on the raw page data and second bin identifiers may be identified for the memory cells of the wordline based on the decoded page data. Cell-level statistics may be accumulated based on the first bin identifiers and the second bin identifiers, and a gradient may be determined for respective read levels based on decoding results for each of the pages and the cell-level statistics. Settings for the read levels may be configured in the flash memory device based on the determined gradients.

US Patent:

20200335173, Oct 22, 2020

Filed:

Jul 6, 2020

Appl. No.:

16/921804

Inventors:

- San Jose CA, US
Aldo Giovanni COMETTI - San Diego CA, US
Richard Leo GALBRAITH - Rochester MN, US
Jonas Andrew GOODE - Lake Forest CA, US
Niranjay RAVINDRAN - Rochester MN, US
Anthony Dwayne WEATHERS - San Diego CA, US

International Classification:

G11C 16/34
G06F 3/06
G11C 11/56
G11C 29/02
G06F 11/10

Abstract:

Systems and methods for read level tracking and optimization are described. Pages from a wordline of a flash memory device read and the raw page data read from the wordline may be buffered in a first set of buffers. The raw page data for each of the pages may be provided to a decoder for decoding and the decoded page data for each of the pages buffered in a second set of buffers. First bin identifiers may be identified for memory cells of the wordline based on the raw page data and second bin identifiers may be identified for the memory cells of the wordline based on the decoded page data. Cell-level statistics may be accumulated based on the first bin identifiers and the second bin identifiers, and a gradient may be determined for respective read levels based on decoding results for each of the pages and the cell-level statistics. Settings for the read levels may be configured in the flash memory device based on the determined gradients.

US Patent:

20190339904, Nov 7, 2019

Filed:

May 4, 2018

Appl. No.:

15/971869

Inventors:

- San Jose CA, US
Chandan Mishra - Irvine CA, US
Amir Hossein Gholamipour - Anaheim CA, US
Aldo Giovanni Cometti - San Diego CA, US
Namhoon Yoo - Anaheim CA, US

International Classification:

G06F 3/06
G06F 12/1009

Abstract:

Aspects of the present disclosure provide systems and methods for operating a solid state drive (SSD) using two-level indirection architecture. The SSD receives a command to perform a data operation in a NAND array and a logical address for the data operation. The SSD then converts the logical address to a physical address using a two-stage logical-to-physical (L2P) mapping table that includes a first stage stored in a byte-rewritable memory and a second stage stored in a block-erasable non-volatile memory (NVM). The SSD performs the data operation in the NAND array based on the physical address. The byte-rewritable memory may any byte-rewritable persistent memory. The block-erasable low latency NVM may be a flash memory that has lower latency than NAND array.

US Patent:

20190214101, Jul 11, 2019

Filed:

Mar 14, 2019

Appl. No.:

16/354039

Inventors:

- San Jose CA, US
Aldo Giovanni Cometti - San Diego CA, US
Richard Leo Galbraith - Rochester MN, US
Jonas Andrew Goode - Lake Forest CA, US
Niranjay Ravindran - Rochester MN, US
Anthony Dwayne Weathers - San Diego CA, US

International Classification:

G11C 16/34
G06F 3/06

Abstract:

Systems and methods for read level tracking and optimization are described. Pages from a wordline of a flash memory device read and the raw page data read from the wordline may be buffered in a first set of buffers. The raw page data for each of the pages may be provided to a decoder for decoding and the decoded page data for each of the pages buffered in a second set of buffers. First bin identifiers may be identified for memory cells of the wordline based on the raw page data and second bin identifiers may be identified for the memory cells of the wordline based on the decoded page data. Cell-level statistics may be accumulated based on the first bin identifiers and the second bin identifiers, and a gradient may be determined for respective read levels based on decoding results for each of the pages and the cell-level statistics. Settings for the read levels may be configured in the flash memory device based on the determined gradients.