Andrew Scott Ross

US Patent:

6360433, Mar 26, 2002

Filed:

Sep 19, 2000

Appl. No.:

09/664938

Inventors:

Andrew C. Ross - San Diego CA 92128

International Classification:

H05K 334

US Classification:

29840, 29832, 257685, 257686

Abstract:

A chip module comprising a chip array which includes an interconnect substrate having opposed, generally planar surfaces and a first interconnect pad array disposed on at least one of the surfaces thereof. Attached to the interconnect substrate is at least one integrated circuit chip of the chip array which is electrically connected to the first interconnect pad array. The chip module further comprises a package which itself comprises a main body defining a cavity sized and configured to receive the chip array and having a generally planar interconnect shelf which extends within the cavity and includes a second interconnect pad array disposed thereon. The package also includes a lid which is attachable to the main body. The chip array is insertable into the cavity such that the first and second interconnect pad arrays are in aligned contact with each other and the attachment of the lid to the main body encloses and seals the chip array within the package.

US Patent:

6437433, Aug 20, 2002

Filed:

Mar 24, 2000

Appl. No.:

09/535641

Inventors:

Andrew C. Ross - Ramona CA 92065

International Classification:

H01L 2348

US Classification:

257692, 257698, 438125

Abstract:

A stackable integrated circuit chip package comprising an interconnect sub-assembly which includes an interconnect substrate having first, second and third conductive pad arrays disposed thereon. The interconnect sub-assembly also includes a first rail member which is attached to the interconnect substrate and has a fourth conductive pad array disposed thereon, and a second rail member which is also attached to the interconnect substrate and has a fifth conductive pad array disposed thereon. The fourth and fifth conductive pad arrays are electrically connected to respective ones of the second and third conductive pad arrays of the interconnect substrate. In addition to the interconnect sub-assembly, the chip package of the present invention includes an integrated circuit chip which is electrically connected to the first conductive pad array of the interconnect substrate of the interconnect sub-assembly.

US Patent:

7372044, May 13, 2008

Filed:

May 17, 2006

Appl. No.:

11/436288

Inventors:

Andrew Ross - Rancho Santa Fe CA, US

International Classification:

A61L 2/10
A61L 9/20

US Classification:

25045511, 250504 R, 2504611, 250365, 422 24, 422121

Abstract:

Techniques for sterilizing a fomite are disclosed. A UV sterilization apparatus includes a housing for enveloping a fomite inside the housing. The housing is composed of a material that prevents transmission of electromagnetic radiation in the ultraviolet range. Attached to the housing is a closure element, and the closure element is also composed of a material that prevents transmission of electromagnetic radiation in the UV range but allows transmission of electromagnetic radiation in the visual range. An ultraviolet light source is attached to an internal surface of the housing or an internal surface of the closure element, and the light source sterilizes the fomite enclosed inside the housing by transmitting ultraviolet electromagnetic radiation towards the fomite.

US Patent:

20030113998, Jun 19, 2003

Filed:

Dec 17, 2001

Appl. No.:

10/024389

Inventors:

Andrew Ross - Ramona CA, US

International Classification:

H01L021/44

US Classification:

438/678000

Abstract:

A connector for use in a chip stack including at least first and second stacked packaged chips which each comprise a package body having a plurality of leads extending therefrom. The connector comprises a substrate which is preferably fabricated from an insulating material. Attached to the substrate are a plurality of flex tabs which extend in spaced relation to each other, and are each preferably fabricated from a conductive material such as aluminum. The flex tabs are each shaped to define an arcuately contoured first portion which is electrically connectable to a respective one of the leads of the first packaged chip, and an integral, generally flat second portion which extends along a portion of the substrate and is electrically connectable to a corresponding one of the leads of the second packaged chip.

US Patent:

20090123331, May 14, 2009

Filed:

Nov 20, 2008

Appl. No.:

12/275173

Inventors:

Andrew Ross - Rancho Santa Fe CA, US

International Classification:

A61L 2/10
B01J 19/12

US Classification:

422 24, 4221863, 422105

Abstract:

Techniques for sterilizing a fomite are disclosed. A UV sterilization apparatus includes a housing for enveloping a fomite inside the housing. The housing is composed of a material that prevents transmission of electromagnetic radiation in the ultraviolet range. Attached to the housing is a closure element, and the closure element is also composed of a material that prevents transmission of electromagnetic radiation in the UV range but allows transmission of electromagnetic RADIATION in the visual range. An ultraviolet light source is attached to an internal surface of the housing or an internal surface of the closure element, and the light source sterilizes the fomite enclosed inside the housing by transmitting ultraviolet electromagnetic radiation towards the fomite.

US Patent:

62227378, Apr 24, 2001

Filed:

Apr 23, 1999

Appl. No.:

9/298664

Inventors:

Andrew C. Ross - San Diego CA

Assignee:

Dense-Pac Microsystems, Inc. - Garden Grove CA

International Classification:

H01L 23043

US Classification:

361767

Abstract:

A chip module comprising a chip array which includes an interconnect substrate having opposed, generally planar surfaces and a first interconnect pad array disposed on at least one of the surfaces thereof. Attached to the interconnect substrate is at least one integrated circuit chip of the chip array which is electrically connected to the first interconnect pad array. The chip module further comprises a package which itself comprises a main body defining a cavity sized and configured to receive the chip array and having a generally planar interconnect shelf which extends within the cavity and includes a second interconnect pad array disposed thereon. The package also includes a lid which is attachable to the main body. The chip array is insertable into the cavity such that the first and second interconnect pad arrays are in aligned contact with each other and the attachment of the lid to the main body encloses and seals the chip array within the package.