Antonio D Marques

US Patent:

7551020, Jun 23, 2009

Filed:

May 31, 2007

Appl. No.:

11/755955

Inventors:

Dipankar Bhattacharya - Macungie PA, US
Makeshwar Kothandaraman - Whitehall PA, US
John C. Kriz - Palmerton PA, US
Antonio M. Marques - Newark NJ, US
Bernard L. Morris - Emmaus PA, US

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

G05F 1/10
G05F 3/02

US Classification:

327538, 327540, 327541, 327543

Abstract:

A compensation circuit for compensating an output impedance of at least a first MOS device over PVT variations to which the first MOS device may be subjected includes a first current source generating a first current having a value which is substantially constant and a second current source generating a second current having a value which is programmable as a function of at least one control signal presented to the second current source. A comparator is connected to respective outputs of the first and second current sources and is operative to measure a difference between the respective values of the first and second currents and to generate an output signal indicative of relative magnitudes of the first current and the second current. A processor connected in a feedback arrangement between the comparator and the second current source receives the output signal generated by the comparator and generates the control signal for controlling the second current as a function of the output signal. The processor is operative to control the value of the second current so that the second current is substantially equal to the first current.

US Patent:

8373441, Feb 12, 2013

Filed:

Sep 20, 2011

Appl. No.:

13/236914

Inventors:

John A. Milinichik - Allentown PA, US
Peter J. Nicholas - Philadelphia PA, US
Carol A. Huber - Macungie PA, US
Antonio M. Marques - Newark NJ, US
Daniel J. Delpero - Allentown PA, US

Assignee:

LSI Corporation - Milpitas CA

International Classification:

H01L 25/00
H03K 19/00

US Classification:

326101, 326 41, 326 47

Abstract:

Described embodiments provide for a semiconductor device comprising a core and one or more input/output (I/O) buffers surrounding the core. The I/O buffers are adapted to transfer signals associated with core circuitry of the core. The I/O buffers comprise I/O cells having a first orientation and I/O cells having a second orientation. Each I/O cell has a corresponding translator having low voltage transistors in a corresponding footprint. The low voltage transistors in the first orientation I/O cells have the first orientation, and the low voltage transistors in the second orientation I/O cells have the first orientation. The footprints of the first orientation I/O cells and the second orientation I/O cells are compatible with one another.