Autumn J Niu

US Patent:

6401142, Jun 4, 2002

Filed:

May 24, 1999

Appl. No.:

09/317258

Inventors:

Robert Alan Williams - Cupertino CA
Autumn Jane Niu - Sunnyvale CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 300

US Classification:

710 14, 710 5, 710 58, 710129, 709209

Abstract:

A network interface for a workstation is configured to supply data to a host bus. A bus interface unit is configured to output the data frame onto the host bus based on a master or slave transfer request to access the buffer memory. The slave request to access the buffer memory may be in the form of either an I/O mapped or memory mapped request. A memory management unit includes request logic to receive the master and slave transfer requests and to generate a generic request to access the buffer memory. The memory management unit is configured to transfer the data frame between the buffer memory and the host bus in response to the generic request. The memory management unit effectively accesses stored data independent from the type of data transfer mode. Notably, the modes of data transfer, master or slave, can be changed within the transfer of a single frame, on a per-byte basis.

US Patent:

6424591, Jul 23, 2002

Filed:

May 28, 1999

Appl. No.:

09/321843

Inventors:

Ching Yu - Santa Clara CA
Autumn Jane Niu - Sunnyvale CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 1200

US Classification:

36523009, 711101

Abstract:

A novel method of providing a host with assess to a buffer memory in a network interface in FIFO and SRAM modes of operation. A decoder decodes whether the host issues an SRAM-type access request or a FIFO-type access request to perform access to the buffer memory. In response to the FIFO-type access request, pointers to the memory are controlled so as to perform sequential addressing of the buffer memory. In response to the SRAM-type request, the pointers are controlled so as to perform random access addressing of the buffer memory.

US Patent:

6473818, Oct 29, 2002

Filed:

Sep 9, 1998

Appl. No.:

09/150038

Inventors:

Autumn J. Niu - Sunnyvale CA
Po-shen Lai - San Jose CA
Jerry Chun-Jen Kuo - San Jose CA
John Chiang - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 1330

US Classification:

710129, 710128, 710131, 711168, 711 61, 711150

Abstract:

A network interface device includes a random access memory used as a transmit and receive buffer for transmission and reception of data frames between a host computer bus and a packet switched network. The network interface device includes read and write controllers for each of the transmit and receive buffers, where each write controller operates in a clock domain separate from the corresponding read controller. Read and write counters are each implemented as gray code counters that increment a corresponding pointer value by changing a single bit. A synchronization circuit selectively sets a full or empty flag based on an asynchronous comparison of the read and write pointer values. Use of gray code counters for the read pointer value and write pointer value ensures accurate comparisons in a multi-clock environment.

US Patent:

6516371, Feb 4, 2003

Filed:

May 27, 1999

Appl. No.:

09/320580

Inventors:

Po-Shen Lai - San Jose CA
Autumn J. Niu - Sunnyvale CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 1314

US Classification:

710129, 710 4, 710 33

Abstract:

A network interface device includes a random access memory used as a transmit and receive buffer for transmission and reception of data between a host computer bus and a packet switched network. The network interface device includes a read controller and read offset register that stores read pointer information. The host CPU programs the read offset register to any particular value so that the read controller will read data from a desired starting point. In this manner, the host CPU is able to skip parts of a frame stored in the random access memory.

US Patent:

6542512, Apr 1, 2003

Filed:

Jul 2, 1999

Appl. No.:

09/346745

Inventors:

Jenny Liu Fischer - Mountain View CA 94040
Ching Yu - Santa Clara CA 95051
Jerry Chun-Jen Kuo - San Jose CA 95123
Po-Shen Lai - San Jose CA 95123
Autumn Jane Niu - Sunnyvale CA 94086
Ian Lam - Fremont CA 94538

International Classification:

H04L 1228

US Classification:

370412

Abstract:

A network switch in a packet switched network includes a plurality of network switch ports, each configured for sending and receiving data packets between a medium interface and the network switch. The network switch port includes an IEEE 802. 3 compliant transmit state machine and receive state machine configured for transmitting and receiving network data to and from a medium interface, such as a reduced medium independent interface, respectively. The network switch port also includes a memory management unit configured for selectively transferring the network data between the transmit and receive state machines and a random access transmit buffer and a random access receive buffer, respectively. The transmit state machine outputs a flush transmit buffer signal to the transmit memory management unit in response to a detected error in transmitting the transmit data. The transmit memory management unit, in response to the flush transmit buffer signal, sets an incremented transmit buffer pointer value to a buffer pointer value corresponding to a next transmit data stored in the transmit buffer.

US Patent:

6625157, Sep 23, 2003

Filed:

May 20, 1999

Appl. No.:

09/314977

Inventors:

Autumn Jane Niu - Sunnyvale CA
Jenny Liu Fischer - Mountain View CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H04L 1228

US Classification:

37039571, 3703957, 37039572, 370389, 370390, 370396, 370397, 709104, 709215, 709216, 710 22, 710 23, 710112

Abstract:

A network switch in a packet switched network includes a plurality of network switch ports, each configured for sending and receiving data packets between a medium interface and the network switch. The network switch port includes an IEEE 802. 3 compliant transmit state machine and receive state machine configured for transmitting and receiving network data to and from a medium interface, such as a reduced medium independent interface, respectively. The network switch port also includes a memory management unit configured for selectively transferring the network data between the transmit and receive state machines and a random access transmit buffer and a random access receive buffer, respectively. The memory management unit transfers the network data between the transmit and receive state machines and the respective buffers based on prescribed interface protocol signals between the memory management unit and the transmit and receive state machines. Hence, the memory management unit and the transmit and receive state machines transfer data according to a prescribed interface protocol, where a request-based protocol enables data transfers to be performed independent of different clock domains encountered within the network switch port.

US Patent:

6789144, Sep 7, 2004

Filed:

May 27, 1999

Appl. No.:

09/320579

Inventors:

Po-Shen Lai - San Jose CA
Autumn J. Niu - Sunnyvale CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 500

US Classification:

710 57, 710 55, 369 2701, 369 3004

Abstract:

A network interface device includes a random access memory used as a transmit and receive buffer for transmission and reception of data between a host computer bus and a packet switched network. The network interface device includes a memory controller that determines whether a complete frame is stored in the random access memory and also determines an amount of data available to be read from the oldest received frame. A host CPU is able to access this information and determine whether to read the data or read the data at a later time.

US Patent:

20020191606, Dec 19, 2002

Filed:

May 9, 2002

Appl. No.:

10/142022

Inventors:

Shaofeng Wu - Sunnyvale CA, US
Jerry Kuo - San Jose CA, US
Po-Shen Lai - San Jose CA, US
Jian Jin - San Jose CA, US
Autumn Niu - San Jose CA, US

Assignee:

Zarlink Semiconductor V.N. Inc. - Irvine CA

International Classification:

H04L012/28

US Classification:

370/389000

Abstract:

A communication interface for processing errors between network devices. The communication interface includes an output interface of a first network device for generating output control information and parity information of output information transmitted therefrom, and an error-handling interface of a second network device, which error-handling interface is in operative communication with the output interface to process the output control information and the parity information of the output information by, checking parity of the parity information of the output information received from the first network device, terminating the output information when an error in the parity is detected, and recovering a boundary of the output information when an error in the output control information is detected.