Autumn J Niu

US Patent:

6401142, Jun 4, 2002

Filed:

May 24, 1999

Appl. No.:

09/317258

Inventors:

Robert Alan Williams - Cupertino CA
Autumn Jane Niu - Sunnyvale CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 300

US Classification:

710 14, 710 5, 710 58, 710129, 709209

Abstract:

A network interface for a workstation is configured to supply data to a host bus. A bus interface unit is configured to output the data frame onto the host bus based on a master or slave transfer request to access the buffer memory. The slave request to access the buffer memory may be in the form of either an I/O mapped or memory mapped request. A memory management unit includes request logic to receive the master and slave transfer requests and to generate a generic request to access the buffer memory. The memory management unit is configured to transfer the data frame between the buffer memory and the host bus in response to the generic request. The memory management unit effectively accesses stored data independent from the type of data transfer mode. Notably, the modes of data transfer, master or slave, can be changed within the transfer of a single frame, on a per-byte basis.

US Patent:

61050792, Aug 15, 2000

Filed:

Dec 18, 1997

Appl. No.:

8/993058

Inventors:

Jerry Chun-Jen Kuo - San Jose CA
Po-Shen Lai - San Jose CA
Autumn Jane Niu - Sunnyvale CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 1314
G06F 1324
G06F 1328

US Classification:

710 25

Abstract:

A network interface device minimizes access latency in initiating a DMA transfer request by selectively supplying a long bit comparison result, generated in a write controller configured for writing data into a buffer memory, directly to a read controller based on a determination that the buffer memory stores less than one complete frame. The media access controller determines the length of the data frame, and supplies the determined length to the write controller. The write controller compares the determined length to a prescribed threshold, and outputs a long bit value for storage in a buffer memory location contiguous with the stored data frame. The long bit can then be used to select a receive buffer threshold optimized for larger frames. If less than one complete frame is stored in the buffer memory, the write controller outputs the long bit information to the read controller, enabling the read controller to initiate a DMA transfer request, using a threshold selected based on the long-bit information, prior to storage of the complete data frame in the buffer memory.

US Patent:

61283088, Oct 3, 2000

Filed:

Dec 18, 1997

Appl. No.:

8/993063

Inventors:

Jerry Chun-Jen Kuo - San Jose CA
Autumn Jane Niu - Sunnyvale CA
Po-Shen Lai - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H04L 1254
H04L 12413

US Classification:

370428

Abstract:

A network interface device includes a random access memory used as a transmit and receive buffer for transmission and reception of data frames between a host computer bus and a packet switched network. The network interface device includes read and write controllers for each of the transmit and receive buffers, where each write controller operates in a clock domain separate from the corresponding read controller. The memory management unit also includes a synchronization circuit that controls arbitration for accessing the random access memory between the read and write controllers. The synchronization circuit determines the presence of a stored frame in the random access memory by asynchronously comparing write counter and read counter values stored in gray code counters, where each counter is configured for changing a single bit of a counter value in response to an increment signal. Use of gray code counters enables asynchronous comparisons to be made between the two counter values, independent of the host computer bus clock domain and the network clock domain.

US Patent:

62161938, Apr 10, 2001

Filed:

Sep 3, 1998

Appl. No.:

9/146252

Inventors:

Po-Shen Lai - San Jose CA
Autumn Jane Niu - Sunnyvale CA
Jerry Chun-Jen Kuo - San Jose CA
John M. Chiang - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 1300
G06F 1338

US Classification:

710129

Abstract:

A network interface includes a multiplexer that selectively supplies either a stored address from an address holding register, or a reload address from a reload address holding register, to a random access buffer memory based on a done delay signal (DMA_DONE_DLY). The done delay signal is generated by an advance signal generator in response to detection of a target initiated termination request on the PCI bus during a DMA data transfer from the random access buffer memory to the target. if the PCI bus transfer is interrupted, the reload address is supplied to the random access buffer memory to enable data output holding registers to be reloaded with the data lost by the target during the interrupted DMA transfer. The array of data output holding registers are capable of recovering from the interrupted PCI bus transfer and output the data set which the target (e. g. , the host system memory) expects to receive.

US Patent:

61547964, Nov 28, 2000

Filed:

Sep 3, 1998

Appl. No.:

9/146168

Inventors:

Jerry Chun-Jen Kuo - San Jose CA
Autumn J. Niu - Sunnyvale CA
Po-Shen Lai - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 1314
G06F 1300
G06F 1200
H04L 1228
H04L 1256

US Classification:

710 52

Abstract:

A network interface device includes a random access memory used as a transmit and receive buffer for transmission and reception of data frames between a host computer bus and a packet switched network. The network interface device includes read and write controllers for each of the transmit and receive buffers, where each write controller operates in a clock domain separate from the corresponding read controller. The read and write controllers output status information corresponding to the reading or writing of a stored data frame in the receive buffer. The memory management unit includes a synchronization circuit, which arbitrates updates to the holding registers by the read and write controllers based on the asynchronously determined presence of at least one stored data frame.

US Patent:

61611603, Dec 12, 2000

Filed:

Sep 3, 1998

Appl. No.:

9/146163

Inventors:

Autumn J. Niu - Sunnyvale CA
Jerry Chun-Jen Kuo - San Jose CA
Po-shen Lai - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 1336
G06F 1312
G06F 1576
H04L 1254
H04L 12413

US Classification:

710129

Abstract:

A network interface device includes a random access transmit buffer and a random access receive buffer for transmission and reception of transmission and receive data frames between a host computer bus and a packet switched network. The network interface device includes a memory management unit having read and write controllers for each of the transmit and receive buffers, where each write controller operates in a clock domain separate from the corresponding read controller. The memory management unit also includes a synchronization circuit that controls arbitration for accessing the random access memories between the read and write controllers. The synchronization circuit asynchronously monitors the amount of data stored in the random access transmit and receive buffer by asynchronously comparing write pointer and read pointer values stored in gray code counters, where each counter is configured for changing a single bit of a counter value in response to an increment signal. A descriptor management unit is used to control DMA reading and writing of transmit data and receive data from and to system memory, respectively, based on descriptor lists, respectively. A pipelining architecture also optimizes transfer of data between the buffers, the PCI bus, and the media access controller.

US Patent:

60617683, May 9, 2000

Filed:

Dec 18, 1997

Appl. No.:

8/993891

Inventors:

Jerry Chun-Jen Kuo - San Jose CA
Autumn Jane Niu - Sunnyvale CA
Po-Shen Lai - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 1300

US Classification:

711156

Abstract:

A network interface device includes a random access memory used as a transmit and receive buffer for transmission and reception of data frames between a host computer bus and a packet switched network. The network interface device includes read and write controllers for each of the transmit and receive buffers, where each write controller operates in a clock domain separate from the corresponding read controller. The memory management unit also includes a synchronization circuit that controls arbitration for accessing the random access memory between the read and write controllers. The synchronization circuit determines the presence of a stored frame in the random access memory by asynchronously comparing write counter and read counter values stored in gray code counters, where each counter is configured for changing a single bit of a counter value in response to an increment signal. The determined presence of one or more stored data frames is used to arbitrate storage of tracking information by either the read controller or the write controller into a holding register used to determine a read status for the random access memory.

US Patent:

60470011, Apr 4, 2000

Filed:

Dec 18, 1997

Appl. No.:

8/993056

Inventors:

Jerry Chun-Jen Kuo - San Jose CA
Po-Shen Lai - San Jose CA
Autumn Jane Niu - Sunnyvale CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H04L 1228
H04L 1256
H04L 1254

US Classification:

370428

Abstract:

A network interface device having a random access memory for buffering data between a host bus interface and a media access controller includes a buffer controller configured for storing a data frame in combination with tracking and status information associated with the storage of the data frame. The memory controller is configured for writing transmit frame data received from a host bus into the random access memory, and generating tracking information based on transfer status signals corresponding to the transfer of the data frame from either a master transfer mode or a slave transfer mode. Hence, the amount of logic associated with generating the tracking, control and/or status information is independent of the nature of the transfer from the host bus. The tracking and status information is stored in memory locations contiguous with the data frame to enable a read controller to access the status information and the corresponding data frame as a single data unit. A second write controller for data received from the media access controller stores the received data frame and the corresponding status information from the media access controller in contiguous memory locations in a receive buffer to form a single data unit.