Appliedmicro Apr 2012 - Apr 2013
Senior Design Engineer
Qualcomm Apr 2012 - Apr 2013
Design Engineer
Lsi Corporation Jun 2010 - Apr 2012
Design Engineer
Uc Santa Cruz Sep 2007 - Mar 2010
Graduate Student
Nasa Ames Research Center Sep 2009 - 2010
Intern
Education:
University of California, Santa Cruz 2007 - 2010
Masters, Engineering
Zhejiang University 2002 - 2006
Bachelors, Electrical Engineering
University of California
Skills:
Simulations Mixed Signal Cadence Virtuoso Analog Fpga Matlab Labview
Karthik M. Sadhasivam - Sunnyvale CA, US Eric M. Trehus - San Jose CA, US Anders K. Fung - Union City CA, US Bin Liang - San Jose CA, US Nicholas R. Leavy - Palo Alto CA, US
Assignee:
Cisco Technology, Inc. - San Jose CA
International Classification:
G06F 15/16
US Classification:
709246, 370392, 3703956
Abstract:
A method and apparatus for virtual application of features to electronic messages is disclosed. When a device applies a set of features to an electronic message, one or more of the features may be virtually applied instead of actually applied. For example, instead of encrypting a payload portion of a packet and adding an encryption header, the packet may not be encrypted. However, an appropriate encryption header may still be included in the packet such that the packet appears to have been encrypted when other features are applied. Prior to sending the packet, the payload portion is actually encrypted, such as by using a hardware accelerator. Some implementations may use a dual processor router, in which the input/output processor controls the hardware accelerator, the routing processor performs the virtual application of a feature, and prior to sending the packet the input/output processor actually applies the virtually applied feature.
Programmable Resistance-Modulated Write Assist For A Memory Device
Jason T. Su - Los Altos CA, US Bin Liang - Sunnyvale CA, US
Assignee:
APPLIED MICRO CIRCUITS CORPORATION - Sunnyvale CA
International Classification:
G11C 7/10
US Classification:
36518916
Abstract:
Providing for improved write processes of a semiconductor memory are disclosed herein. By way of example, a programmable write assist can be provided that includes partially discharging a supply voltage applied to a memory cell. Partially discharging the supply voltage can improve write speeds to the memory cell, as well as improve reliability of the write process. A write assist circuit can cause the discharging in response to a resistance-modulated signal. Moreover, the resistance-modulated signal can be configured to control an amount or speed of the discharging of the supply voltage. Further, modulation control can be provided to mitigate discharging of the supply voltage beyond a target level, to reduce data loss in a target data cell or an adjacent data cell.