Brian L Singletary

US Patent:

7863724, Jan 4, 2011

Filed:

Feb 12, 2008

Appl. No.:

12/029574

Inventors:

Daniel Douriet - Round Rock TX, US
Francesco Preda - New Braunfels TX, US
Brian L. Singletary - Austin TX, US
Lloyd A. Walls - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 23/52

US Classification:

257691, 257698, 257700, 257701, 257702, 257703, 257E23006, 257E23011, 257E2302, 257E23067, 257E23079

Abstract:

A circuit substrate uses post-fed top side power supply connections to provide improved routing flexibility and lower power supply voltage drop/power loss. Plated-through holes are used near the outside edges of the substrate to provide power supply connections to the top metal layers of the substrate adjacent to the die, which act as power supply planes. Pins are inserted through the plated-through holes to further lower the resistance of the power supply path(s). The bottom ends of the pins may extend past the bottom of the substrate to provide solderable interconnects for the power supply connections, or the bottom ends of the pins may be soldered to “jog” circuit patterns on a bottom metal layer of the substrate which connect the pins to one or more power supply terminals of an integrated circuit package including the substrate.

US Patent:

8586476, Nov 19, 2013

Filed:

Sep 2, 2010

Appl. No.:

12/874397

Inventors:

Daniel Douriet - Round Rock TX, US
Francesco Preda - New Braunfels TX, US
Brian L. Singletary - Austin TX, US
Lloyd A. Walls - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/44

US Classification:

438667, 438618, 438622, 438624, 438625, 438666, 438674, 438675

Abstract:

A circuit substrate uses post-fed top side power supply connections to provide improved routing flexibility and lower power supply voltage drop/power loss. Plated-through holes are used near the outside edges of the substrate to provide power supply connections to the top metal layers of the substrate adjacent to the die, which act as power supply planes. Pins are inserted through the plated-through holes to further lower the resistance of the power supply path(s). The bottom ends of the pins may extend past the bottom of the substrate to provide solderable interconnects for the power supply connections, or the bottom ends of the pins may be soldered to “jog” circuit patterns on a bottom metal layer of the substrate which connect the pins to one or more power supply terminals of an integrated circuit package including the substrate.

US Patent:

8634877, Jan 21, 2014

Filed:

Apr 9, 2012

Appl. No.:

13/441964

Inventors:

Fallon M. Delco - Austin TX, US
Donna L. Johnson - Pflugerville TX, US
Manjunath N. Mangalur - Bangalore, IN
Brian L. Singletary - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H04B 1/38
H04M 1/00

US Classification:

455567, 455417

Abstract:

Mechanisms for modifying a notification mode for notifying a user of an incoming communication is provided. In a first communication device, an incoming communication from a second communication device is received. A total number of received incoming communications from the second communication device within a predetermined period of time is determined and compared to a first threshold. In response to the total number of received incoming communications from the second communication device within the predetermined period of time meeting or exceeding the first predetermined threshold, a notification mode of the first communication device is modified to be different from a current default notification mode of the first communication device for incoming communications from the second communication device. A notification of the incoming communication from the second communication device is generated using the modified notification mode of the first communication device.

US Patent:

20060214190, Sep 28, 2006

Filed:

Mar 22, 2005

Appl. No.:

11/086719

Inventors:

Sungjun Chun - Austin TX, US
Jason Frankel - Wappingers Falls NY, US
Anand Haridass - Austin TX, US
Erich Klink - Schoenaich, DE
Brian Singletary - Austin TX, US

International Classification:

H01L 27/10

US Classification:

257208000

Abstract:

A system and method for reducing noise in a multi-layer ceramic package are provided. With the system and method, additional shielding wires are inserted into the reference planes wherever there are no signal vias present. These additional lines in the reference planes force stronger signal interaction with the reference (vdd/gnd) thereby reducing the interaction between the signals in the signal layers. As a result, the noise present in the signals of the signal layers is reduced.

US Patent:

20070080436, Apr 12, 2007

Filed:

Oct 4, 2006

Appl. No.:

11/538531

Inventors:

Sungjun Chun - Austin TX, US
Jason Frankel - Wappingers Falls NY, US
Anand Haridass - Austin TX, US
Erich Klink - Schoenaich, DE
Brian Singletary - Austin TX, US

International Classification:

H01L 23/495

US Classification:

257668000

Abstract:

A system and method for reducing noise in a multi-layer ceramic package are provided. With the system and method, additional shielding wires are inserted into the reference planes wherever there are no signal vias present. These additional lines in the reference planes force stronger signal interaction with the reference (vdd/gnd) thereby reducing the interaction between the signals in the signal layers. As a result, the noise present in the signals of the signal layers is reduced.

US Patent:

20130316534, Nov 28, 2013

Filed:

Aug 5, 2013

Appl. No.:

13/959003

Inventors:

Francesco Preda - New Braunfels TX, US
Brian L. Singletary - Austin TX, US
Lloyd A. Walls - Austin TX, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - ARMONK NY

International Classification:

H01L 21/768

US Classification:

438667

Abstract:

A circuit substrate uses post-fed top side power supply connections to provide improved routing flexibility and lower power supply voltage drop/power loss. Plated-through holes are used near the outside edges of the substrate to provide power supply connections to the top metal layers of the substrate adjacent to the die, which act as power supply planes. Pins are inserted through the plated-through holes to further lower the resistance of the power supply path(s). The bottom ends of the pins may extend past the bottom of the substrate to provide solderable interconnects for the power supply connections, or the bottom ends of the pins may be soldered to “jog” circuit patterns on a bottom metal layer of the substrate which connect the pins to one or more power supply terminals of an integrated circuit package including the substrate.