Carl J Mies

US Patent:

7382790, Jun 3, 2008

Filed:

Jul 10, 2003

Appl. No.:

10/617148

Inventors:

Bruce Gregory Warren - Poulsbo WA, US
William P. Goodwin - Bothell WA, US
Carl Mies - Snohomish WA, US
Bruce E. Johnson - Federal Way WA, US
Michael L. White - Oak Harbor WA, US
Warren Eng - Renton WA, US

Assignee:

Emulex Design & Manufacturing Corporation - Costa Mesa CA

International Classification:

H04L 12/28

US Classification:

370401, 370389, 370422

Abstract:

Methods and apparatus for switching Fibre Channel Arbitrated Loop Systems is provided between a plurality of Fibre Channel Loop devices. In one aspect of the invention, the system switches based at least in part on arbitrated loop primitives. An exemplary interconnect system may include a first port and a second port, both including port logic to monitor certain arbitrated loop primitives, a connectivity apparatus, a route determination apparatus including a routing table consisting of ALPA addresses and their associated ports, the route determination apparatus coupled to each port and the connectivity apparatus, where the connectivity apparatus creates paths between the ports based on arbitrated loop primitives. In one embodiment, the connectivity apparatus is a crossbar switch. Examples of the arbitrated loop primitives that cause the switch to create paths between ports includes one or more of the following: ARB, OPN and CLS.

US Patent:

7397788, Jul 8, 2008

Filed:

Jul 10, 2003

Appl. No.:

10/616866

Inventors:

Carl Mies - Snohomish WA, US
Bruce Gregory Warren - Poulsbo WA, US

Assignee:

Emulex Design & Manufacturing Corporation - Costa Mesa CA

International Classification:

H04L 12/28
H04L 12/26

US Classification:

370351, 370230, 370404

Abstract:

Methods and apparatus for switching Fibre Channel Arbitrated Loop Systems is provided between a plurality of Fibre Channel Loop devices. In one aspect of the invention, the system switches based at least in part on arbitrated loop primitives. An exemplary interconnect system may include a first port and a second port, both including port logic to monitor certain arbitrated loop primitives, a connectivity apparatus, a route determination apparatus including a routing table consisting of ALPA addresses and their associated ports, the route determination apparatus coupled to each port and the connectivity apparatus, where the connectivity apparatus creates paths between the ports based on arbitrated loop primitives. In one embodiment, the connectivity apparatus is a crossbar switch. Examples of the arbitrated loop primitives that cause the switch to create paths between ports includes one or more of the following: ARB, OPN and CLS.

US Patent:

7630300, Dec 8, 2009

Filed:

Jul 10, 2003

Appl. No.:

10/617149

Inventors:

Bruce Gregory Warren - Poulsbo WA, US
William Goodwin - Bothell WA, US
Carl Mies - Snohomish WA, US
Thomas Hammond-Doel - Everett WA, US
Michael L. White - Oak Harbor WA, US

Assignee:

Emulex Design & Manufacturing Corporation - Costa Mesa CA

International Classification:

H04L 12/28
H04J 14/00

US Classification:

370222, 370351, 370404, 370406, 398 3, 398 59

Abstract:

Methods and apparatus for switching Fiber Channel Arbitrated Loop Systems is provided between a plurality of Fiber Channel Loop devices. In one aspect of the invention, the system switches based at least in part on arbitrated loop primitives. An exemplary interconnect system may include a first port and a second port, both including port logic to monitor certain arbitrated loop primitives, a connectivity apparatus, a route determination apparatus including a routing table consisting of ALPA addresses and their associated ports, the route determination apparatus coupled to each port and the connectivity apparatus, where the connectivity apparatus creates paths between the ports based on arbitrated loop primitives. In one embodiment, the connectivity apparatus is a crossbar switch. Examples of the arbitrated loop primitives that cause the switch to create paths between ports includes one or more of the following: ARB, OPN and CLS.

US Patent:

7660316, Feb 9, 2010

Filed:

Jul 10, 2003

Appl. No.:

10/616862

Inventors:

Bruce Gregory Warren - Poulsbo WA, US
William Goodwin - Bothell WA, US
Carl Mies - Snohomish WA, US
Bruce E. Johnson - Federal Way WA, US
Michael L. White - Oak Harbor WA, US
Warren Eng - Renton WA, US

Assignee:

Emulex Design & Manufacturing Corporation - Costa Mesa CA

International Classification:

H04L 12/28
G06F 11/00

US Classification:

370401, 370223, 370250, 370389, 370412, 370424, 714 2, 714 8, 714100

Abstract:

Methods and apparatus for switching Fibre Channel Arbitrated Loop Systems is provided between a plurality of Fibre Channel Loop devices. In one aspect of the invention, the system switches based at least in part on arbitrated loop primitives. An exemplary interconnect system may include a first port and a second port, both including port logic to monitor certain arbitrated loop primitives, a connectivity apparatus, a route determination apparatus including a routing table consisting of ALPA addresses and their associated ports, the route determination apparatus coupled to each port and the connectivity apparatus, where the connectivity apparatus creates paths between the ports based on arbitrated loop primitives. In one embodiment, the connectivity apparatus is a crossbar switch. Examples of the arbitrated loop primitives that cause the switch to create paths between ports includes one or more of the following: ARB, OPN and CLS.

US Patent:

7664018, Feb 16, 2010

Filed:

Jul 1, 2003

Appl. No.:

10/612753

Inventors:

Bruce Gregory Warren - Poulsbo WA, US
William Goodwin - Bothell WA, US
Carl Mies - Snohomish WA, US
Michael L. White - Oak Harbor WA, US
Warren Eng - Renton WA, US
Bruce E. Johnson - Federal Way WA, US

Assignee:

Emulex Design & Manufacturing Corporation - Costa Mesa CA

International Classification:

H04L 12/28
H04J 14/00

US Classification:

370230, 370250, 370351, 370404, 370424, 370453, 370258, 398 3, 398 59

Abstract:

Methods and apparatus for switching Fiber Channel Arbitrated Loop Systems is provided between a plurality of Fiber Channel Loop devices. In one aspect of the invention, the system switches based at least in part on arbitrated loop primitives. An exemplary interconnect system may include a first port and a second port, both including port logic to monitor certain arbitrated loop primitives, a connectivity apparatus, a route determination apparatus including a routing table consisting of ALPA addresses and their associated ports, the route determination apparatus coupled to each port and the connectivity apparatus, where the connectivity apparatus creates paths between the ports based on arbitrated loop primitives. In one embodiment, the connectivity apparatus is a crossbar switch. Examples of the arbitrated loop primitives that cause the switch to create paths between ports includes one or more of the following: ARB, OPN and CLS.

US Patent:

20130346799, Dec 26, 2013

Filed:

Aug 26, 2013

Appl. No.:

14/010468

Inventors:

Carl Joseph MIES - Snohomish WA, US
William Eugene MORGAN - Seattle WA, US
William Patrick GOODWIN - Woodinville WA, US

Assignee:

Emulex Design & Manufacturing Corporation - Costa Mesa CA

International Classification:

G06F 11/26

US Classification:

714 28

Abstract:

Embodiments of the invention enable error simulation for system validation. Errors can be simulated by modifying data presented to the processor as well as generating interrupts consistent with the modified data in the ASIC hardware. Modify logic may be added to the ASIC so when the microprocessor attempts to read a specific address, the modify logic may mask one or more of the data bits returned by the requested address. Address, bit mask, and force value data may be stored in registers to determine which address may be modified, the bit location to be modified, and the value that bit location should be changed to. Selection logic may then determine whether data from the modify logic or the unmodified value from an attached device should be sent to the ASIC interface and on to the microprocessor. A timer may also be used to decouple the setup from the test.

US Patent:

20140208162, Jul 24, 2014

Filed:

Mar 24, 2014

Appl. No.:

14/223493

Inventors:

- Costa Mesa CA, US
Carl Joseph Mies - Snohomish WA, US
William Eugene Morgan - Seattle WA, US
William Patrick Goodwin - Woodinville WA, US

Assignee:

Emulex Corporation - Costa Mesa CA

International Classification:

G06F 11/263

US Classification:

714 34

Abstract:

A device, integrated circuit and method for generating simulated errors are disclosed. In the disclosed device, integrated circuit and method, an original data value is read from a memory. The original data value is intercepted by the integrated circuit. The integrated circuit is operable to virtualize an error in the original data value to generate a modified data value. The integrated circuit is also operable to generate an interrupt according to the virtualization. This disclosure may be particularly useful for high-level memory validation.