Cheng Xiaowen Xu

US Patent:

20220359115, Nov 10, 2022

Filed:

Jul 26, 2022

Appl. No.:

17/873509

Inventors:

- Santa Clara CA, US
Rahul JAIN - Gilbert AZ, US
Sai VADLAMANI - Chandler AZ, US
Cheng XU - Chandler AZ, US
Ji Yong PARK - Chandler AZ, US
Junnan ZHAO - Gilbert AZ, US
Seo Young KIM - Chandler AZ, US

International Classification:

H01F 27/32
H01L 23/498
H01F 41/04
H01L 21/48
H01F 27/28

Abstract:

Apparatuses, systems and methods associated with a substrate assembly with an encapsulated magnetic feature for an inductor are disclosed herein. In embodiments, a substrate assembly may include a base substrate, a magnetic feature encapsulated within the base substrate, and a coil, wherein a portion of the coil extends through the magnetic feature. Other embodiments may be described and/or claimed.

US Patent:

20220278038, Sep 1, 2022

Filed:

May 12, 2022

Appl. No.:

17/742816

Inventors:

- Santa Clara CA, US
Kyu Oh Lee - Chandler AZ, US
Yikang Deng - Chandler AZ, US
Zhichao Zhang - Chandler AZ, US
Liwei Cheng - Chandler AZ, US
Andrew James Brown - Phoenix AZ, US
Cheng Xu - Chandler AZ, US
Jiwei Sun - Chandler AZ, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 23/498
H01L 23/00
H01L 21/48

Abstract:

Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a core substrate with a first conductive structure having a first thickness on the core substrate, and a second conductive structure having a second thickness on the core substrate, where the first thickness is different than the second thickness.

US Patent:

20220230951, Jul 21, 2022

Filed:

Apr 7, 2022

Appl. No.:

17/715380

Inventors:

- Santa Clara CA, US
Junnan Zhao - Gilbert AZ, US
Sai Vadlamani - Chandler AZ, US
Ying Wang - Chandler AZ, US
Rahul Jain - Chandler AZ, US
Andrew J. Brown - Chandler AZ, US
Lauren A. Link - Chandler AZ, US
Cheng Xu - Chandler AZ, US
Sheng C. Li - Chandler AZ, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 23/498
H01L 21/48
H01F 27/28
H01F 41/04
H01L 25/16

Abstract:

Methods/structures of forming in-package inductor structures are described. Embodiments include a substrate including a dielectric material, the substrate having a first side and a second side. A conductive trace is located within the dielectric material. A first layer is on a first side of the conductive trace, wherein the first layer comprises an electroplated magnetic material, and wherein a sidewall of the first layer is adjacent the dielectric material. A second layer is on a second side of the conductive trace, wherein the second layer comprises the electroplated magnetic material, and wherein a sidewall of the second layer is adjacent the dielectric material.

US Patent:

20210305154, Sep 30, 2021

Filed:

Mar 25, 2020

Appl. No.:

16/829336

Inventors:

- Santa Clara CA, US
Yikang Deng - Chandler AZ, US
Junnan Zhao - Gilbert AZ, US
Andrew James Brown - Phoenix AZ, US
Cheng Xu - Chandler AZ, US
Kaladhar Radhakrishnan - Chandler AZ, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 23/522
H01L 23/528
H01L 23/532
H01L 49/02

Abstract:

Disclosed herein are magnetic structures in integrated circuit (IC) package supports, as well as related methods and devices. For example, in some embodiments, an IC package support may include a conductive line, a magnetic structure around the conductive line, and material stubs at side faces of the magnetic structure.

US Patent:

20210111166, Apr 15, 2021

Filed:

Dec 21, 2020

Appl. No.:

17/129269

Inventors:

- Santa Clara CA, US
Cheng Xu - Chandler AZ, US
Junnan Zhao - Gilbert AZ, US
Ying Wang - Chandler AZ, US
Meizi Jiao - Chandler AZ, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 25/16
H01L 23/538
H01L 49/02
H01L 23/498
H01L 21/56
H01L 23/528

Abstract:

Microelectronic assemblies, related devices, and methods are disclosed herein. In some embodiments, a microelectronic assembly may include a die having a first surface and an opposing second surface; a capacitor having a surface, wherein the surface of the capacitor is coupled to the first surface of the die; and a conductive pillar coupled to the first surface of the die. In some embodiments, a microelectronic assembly may include a capacitor in a first dielectric layer; a conductive pillar in the first dielectric layer; a first die having a surface in the first dielectric layer; and a second die having a surface in a second dielectric layer, wherein the second dielectric layer is on the first dielectric layer, and wherein the surface of the second die is coupled to the capacitor, to the surface of the first die, and to the conductive pillar.

US Patent:

20210020558, Jan 21, 2021

Filed:

Oct 6, 2020

Appl. No.:

17/064085

Inventors:

- Santa Clara CA, US
Ying Wang - Chandler AZ, US
Cheng Xu - Chandler AZ, US
Chong Zhang - Chandler AZ, US
Junnan Zhao - Gilbert AZ, US

International Classification:

H01L 23/498
H01L 23/538

Abstract:

An electronic device may include a substrate, and the substrate may include one or more layers. The one or more layers may include a first dielectric material and one or more electrical traces. A cavity may be defined in the substrate, and the cavity may be adapted to receive one or more electrical components. One or more lateral traces may extend through a wall of the cavity. The lateral traces may provide electrical communication pathways between the substrate and the electrical components.

US Patent:

20200411413, Dec 31, 2020

Filed:

Jun 27, 2019

Appl. No.:

16/454705

Inventors:

Amruthavalli Pallavi Alur - Tempe AZ, US
Brandon C. Marin - Chandler AZ, US
Yikang Deng - Chandler AZ, US
Liwei Cheng - Chandler AZ, US
Jeremy D. Ecton - Gilbert AZ, US
Andrew J. Brown - Phoenix AZ, US
Lauren A. Link - Mesa AZ, US
Cheng Xu - Chandler AZ, US
Prithwish Chatterjee - Tempe AZ, US
Ying Wang - Chandler AZ, US

International Classification:

H01L 23/48
H01L 23/522
H01L 23/528
H01L 21/768

Abstract:

A substrate for an electronic device may include a first layer, and the first layer may include dielectric material. The first layer may include a first interconnect, and the first interconnect may have a first interconnect profile. The substrate may include a second layer, and the second layer may include dielectric material. The second layer may include a second interconnect, and the second interconnect may have a second interconnect profile. The first interconnect profile may be indicative of a subtractive manufacturing operation and the second interconnect profile may be indicative of an additive manufacturing operation.

US Patent:

20200402884, Dec 24, 2020

Filed:

Jun 19, 2019

Appl. No.:

16/446538

Inventors:

- Santa Clara CA, US
Sergio Antonio Chan Arguedas - Chandler AZ, US
Peng Li - Chandler AZ, US
Chandra Mohan Jha - Tempe AZ, US
Aravindha R. Antoniswamy - Phoenix AZ, US
Cheng Xu - Chandler AZ, US
Junnan Zhao - Gilbert AZ, US
Ying Wang - Chandler AZ, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 23/367
H01L 23/053
H01L 23/498
H01L 23/433

Abstract:

Disclosed herein are vented lids for integrated circuit (IC) packages, as well as related methods and devices. For example, in some embodiments, an IC package may include a package substrate, a lid, and a die between the package substrate and the lid. A vent may extend between the interior surface and the exterior surface of the lid, and the vent may at least partially overlap the die.