Chung Wai Leung

US Patent:

6355524, Mar 12, 2002

Filed:

Aug 15, 2000

Appl. No.:

09/640139

Inventors:

Hsing Ti Tuan - Cupertino CA
Li-Chun Li - Los Gatos CA
Chung Wai Leung - Milpitas CA
Thomas Tong-Long Chang - Santa Clara CA

Assignee:

Mosel Vitelic, Inc. - Hsin Chu

International Classification:

H01L 21336

US Classification:

438257

Abstract:

In a nonvolatile memory, select gates are self-aligned spacers formed on sidewalls of floating/control gate stacks. The same mask ( ) is used to remove the select gate layer from over the source lines ( ), to etch trench insulation in the source line regions, and to dope the source lines. The memory can be formed in and over an isolated substrate region. The source lines can be doped at least partially before the trench insulation is etched, to prevent a short before the source lines and a region isolating the isolated substrate region from below. The memory can be erased by sectors, or alternatively a chip erase operation can be performed to erase all the cells in parallel. Peripheral transistor gates can be formed from the same layer as the select gates. The select gate spacers have extensions to which low resistance contacts can be made from overlying metal lines.

US Patent:

6358807, Mar 19, 2002

Filed:

Feb 15, 2000

Appl. No.:

09/504306

Inventors:

Yih-Feng Chyan - Orlando FL
Chung Leung - Orlando FL

Assignee:

Agere Systems Guardian Corp. - Orlando FL

International Classification:

H01L 21331

US Classification:

438309, 438202, 438511

Abstract:

A BiCMOS semiconductor device and a method of forming same are disclosed. A bipolar transistor region is formed adjacent a CMOS device region within a semiconductor substrate. Carbon is implanted in an amount ranging from about 10 to about 10 cm before forming the base, emitter and collector within the bipolar transistor region to aid in suppressing transient enhanced diffusion. The bipolar transistor region is subject to rapid thermal annealing to aid in suppressing the transient enhanced diffusion.

US Patent:

6451660, Sep 17, 2002

Filed:

Jun 9, 2000

Appl. No.:

09/591037

Inventors:

Yi Ma - Orlando FL
Yih-Feng Chyan - Orlando FL
Chung Wai Leung - Orlando FL
Jane Qian Liu - Orlando FL
Timothy Scott Campbell - Gotha FL

Assignee:

Agere Systems Guardian Corp. - Allentown PA

International Classification:

H01L 2131

US Classification:

438343, 438765, 438770

Abstract:

A bipolar device ( ) includes an oxide layer ( ) which is grown on the surface ( ) of a semiconductor substrate ( ) by immersing the surface in ozonated deionized water. By selecting an appropriate temperature of the water and concentration of the ozone, the thickness of the film can be maintained within fine tolerances from lot to lot, and over the surface of a wafer (W) comprising the substrate.

US Patent:

6566196, May 20, 2003

Filed:

May 15, 2002

Appl. No.:

10/146979

Inventors:

Barbara Haselden - Cupertino CA
Chia-Shun Hsiao - Cupertino CA
Chunchieh Huang - San Jose CA
Jin-Ho Kim - San Jose CA
Chung Wai Leung - Milpitas CA

Assignee:

Mosel Vitelic, Inc. - Hsin Chu

International Classification:

H01L 21336

US Classification:

438257, 438954

Abstract:

In a nonvolatile memory, a floating gate ( ) is covered with ONO ( ), and a control gate polysilicon layer ( ) is formed on the ONO. After the control gate is patterned, the control gate sidewalls are oxidized to form a protective layer ( ) of silicon dioxide. This oxide protects the control gate polysilicon during a subsequent etch of the silicon nitride portion ( ) of the ONO. Therefore, the silicon nitride can be removed with an isotropic etch. A potential damage to the substrate isolation dielectric ( ) is therefore reduced. Other embodiments are also provided.

US Patent:

6537887, Mar 25, 2003

Filed:

Nov 30, 2000

Appl. No.:

09/727325

Inventors:

Yih-Feng Chyan - New Providence NJ
Chung Wai Leung - Orlando FL
Yi Ma - Orlando FL
Demi Nguyen - Orlando FL

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

H01L 218222

US Classification:

438309, 438170, 438189, 438234, 438235, 438236, 438423, 438440, 438506, 257555, 257557, 257565

Abstract:

An integrated circuit and a process for making the same are provided. The circuit has a nitrogen implanted emitter window, wherein the nitrogen has been implanted into the emitter window after the emitter window etch, but prior to the emitter conductor deposition. Nitrogen implantation is expected to minimize oxide growth variation.

US Patent:

6555871, Apr 29, 2003

Filed:

Jan 20, 2000

Appl. No.:

09/488108

Inventors:

Yih-Feng Chyan - Orlando FL
Chung Wai Leung - Orlando FL
Ranbir Singh - Orlando FL

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

H01L 29792

US Classification:

257326, 257318, 257370, 257371

Abstract:

The present invention provides a bipolar transistor for use in increasing a speed of a flash memory cell having a source region and a drain region and first and second complementary tubs. In one embodiment, a base for the bipolar transistor is located in the first complementary tub. The first complementary tub functions as a collector for the bipolar transistor. The bipolar transistor base also uniquely functions as the source region. The bipolar transistors emitter is also located in the first complementary tub and proximate the base. For example, the emitter may be located adjacent the base or actually located in the base. In an additional embodiment, the opposing bases and emitters are located on opposing sides of and proximate to the flash memory cell.

US Patent:

6559055, May 6, 2003

Filed:

Apr 30, 2001

Appl. No.:

09/846123

Inventors:

Hsing Ti Tuan - Cupertino CA
Chung Wai Leung - Milpitas CA

Assignee:

Mosel Vitelic, Inc.

International Classification:

H01L 21336

US Classification:

438692, 438926

Abstract:

Circuit elements (e. g. transistor gates) formed over a semiconductor substrate are protected by adjacent dummy structures during mechanical or chemical mechanical polishing of an overlying dielectric.

US Patent:

6570215, May 27, 2003

Filed:

Jul 18, 2002

Appl. No.:

10/199157

Inventors:

Hsing T. Tuan - Cupertino CA
Vei-Han Chan - San Jose CA
Chung Wai Leung - Milpitas CA
Chia-Shun Hsiao - Hsin-Chu, TW

Assignee:

Mosel Vitelic, Inc. - Hsin Chu

International Classification:

H01L 2362

US Classification:

257315, 438257, 438258, 438259, 438266, 438267, 438296, 438315

Abstract:

In a nonvolatile memory, a floating gate includes a portion of a conductive layer ( ), and also includes conductive spacers ( ). The spacers increase the capacitive coupling between the floating gate and the control gate ( ).