Chung Sau Y T Leung

US Patent:

6358807, Mar 19, 2002

Filed:

Feb 15, 2000

Appl. No.:

09/504306

Inventors:

Yih-Feng Chyan - Orlando FL
Chung Leung - Orlando FL

Assignee:

Agere Systems Guardian Corp. - Orlando FL

International Classification:

H01L 21331

US Classification:

438309, 438202, 438511

Abstract:

A BiCMOS semiconductor device and a method of forming same are disclosed. A bipolar transistor region is formed adjacent a CMOS device region within a semiconductor substrate. Carbon is implanted in an amount ranging from about 10 to about 10 cm before forming the base, emitter and collector within the bipolar transistor region to aid in suppressing transient enhanced diffusion. The bipolar transistor region is subject to rapid thermal annealing to aid in suppressing the transient enhanced diffusion.

US Patent:

6451660, Sep 17, 2002

Filed:

Jun 9, 2000

Appl. No.:

09/591037

Inventors:

Yi Ma - Orlando FL
Yih-Feng Chyan - Orlando FL
Chung Wai Leung - Orlando FL
Jane Qian Liu - Orlando FL
Timothy Scott Campbell - Gotha FL

Assignee:

Agere Systems Guardian Corp. - Allentown PA

International Classification:

H01L 2131

US Classification:

438343, 438765, 438770

Abstract:

A bipolar device ( ) includes an oxide layer ( ) which is grown on the surface ( ) of a semiconductor substrate ( ) by immersing the surface in ozonated deionized water. By selecting an appropriate temperature of the water and concentration of the ozone, the thickness of the film can be maintained within fine tolerances from lot to lot, and over the surface of a wafer (W) comprising the substrate.

US Patent:

6555871, Apr 29, 2003

Filed:

Jan 20, 2000

Appl. No.:

09/488108

Inventors:

Yih-Feng Chyan - Orlando FL
Chung Wai Leung - Orlando FL
Ranbir Singh - Orlando FL

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

H01L 29792

US Classification:

257326, 257318, 257370, 257371

Abstract:

The present invention provides a bipolar transistor for use in increasing a speed of a flash memory cell having a source region and a drain region and first and second complementary tubs. In one embodiment, a base for the bipolar transistor is located in the first complementary tub. The first complementary tub functions as a collector for the bipolar transistor. The bipolar transistor base also uniquely functions as the source region. The bipolar transistors emitter is also located in the first complementary tub and proximate the base. For example, the emitter may be located adjacent the base or actually located in the base. In an additional embodiment, the opposing bases and emitters are located on opposing sides of and proximate to the flash memory cell.

US Patent:

6657281, Dec 2, 2003

Filed:

Aug 3, 2000

Appl. No.:

09/631755

Inventors:

Yih-Feng Chyan - Orlando FL
Chunchieh Huang - Orlando FL
Chung Wai Leung - Orlando FL
Yi Ma - Orlando FL
Shahriar Moinian - Murray Hill NJ

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

H01L 27082

US Classification:

257591, 257565

Abstract:

The present invention provides a bipolar transistor located on a semiconductor wafer substrate. The bipolar transistor may comprise a collector located in the semiconductor wafer substrate, a base located in the collector, and an emitter located on the base and in contact with at least a portion of the base, wherein the emitter has a low K layer located therein. The low K layer may be, for example, located proximate a side of the emitter, or it may be located proximate opposing sides of the emitter. In all embodiments, however, the low K layer does not interfere with the proper functioning of the bipolar transistor, and substantially reduces the emitter-base capacitance typically associated with conventional bipolar transistors.

US Patent:

6815302, Nov 9, 2004

Filed:

Dec 21, 2001

Appl. No.:

10/028614

Inventors:

Alan Sangone Chen - Windermere FL
Yih-Feng Chyan - New Providence NJ
Chung Wai Leung - Milpitas CA
Yi Ma - Orlando FL
William John Nagy - Orlando FL

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

H01L 218228

US Classification:

438323, 438324, 438343, 438365

Abstract:

The present invention provides a method of manufacturing a bipolar transistor. The method may comprise forming a collector in a semiconductor wafer substrate, forming a base in the collector, implanting an oxide region within said collector and over the base, and forming an emitter over the substrate such that the oxide region is located between the emitter and the base.

US Patent:

58438270, Dec 1, 1998

Filed:

Sep 30, 1996

Appl. No.:

8/724128

Inventors:

Richard William Gregor - Winter Park FL
Chung Wai Leung - Orlando FL

Assignee:

Lucent Technologies Inc. - Murray Hill NJ

International Classification:

H01L 21336

US Classification:

438301

Abstract:

A method of suppressing damage to gate dielectrics by reducing the electrical field across the gate dielectric during plasma etching, photoresist stripping, or plasma assisted deposition of the overlying conductor to be etched. Openings in the gate oxide in the vicinity of the gates to be formed place the two conductive layers in contact with each other before the gates are formed and allows for the underlying conductive layer (usually the substrate) to be exposed to the plasma as the overlying unmasked conductive layer (usually polysilicon) is etched away. Preferably, the layer to be etched is deposited to be in contact with the underlying layer at the openings. This technique is applicable to integrated capacitor structures and other susceptible structures with a dielectric layer between two conductors.

US Patent:

58518703, Dec 22, 1998

Filed:

May 9, 1996

Appl. No.:

8/644086

Inventors:

Dayo Alugbin - Windmere FL
Chung Wai Leung - Orlando FL
Joseph Rudolph Radosevich - Orlando FL
Ranbir Singh - Orlando FL
Daniel Mark Wroge - Orlando FL

Assignee:

Lucent Technologies Inc. - Murray Hill NJ

International Classification:

H01L 218242

US Classification:

438239

Abstract:

A novel capacitor design for use in semiconductor integrated circuits is disclosed. The capacitor includes a metal-dielectric-metal stack formed within a window and upon a conductive substrate. Contact to the top plate of the capacitor is through a window within a window, while contact to the bottom plate is achieved by a guard ring which contacts the conductive substrate.

US Patent:

62227645, Apr 24, 2001

Filed:

Dec 13, 1999

Appl. No.:

9/460160

Inventors:

Patrick J. Kelley - Orlando FL
Chung Wai Leung - Orlando FL
Ranbir Singh - Orlando FL

Assignee:

Agere Systems Guardian Corp. - Murray Hill NJ

International Classification:

G11C 1604

US Classification:

36518507

Abstract:

An electrically erasable memory device includes a substrate and a plurality of single poly layer memory cells in the substrate. Each single poly layer memory cell includes a first MOS transistor in a first region in the substrate and spaced apart source and drain regions. Each single poly layer memory cell further includes a capacitor having a first electrode overlying a second region in the substrate and an insulating layer therebetween, and a third region in the second region defining a second electrode. An erasing circuit selectively erases the single poly layer memory cell by supplying a first voltage reference of a first polarity to the spaced apart source and drain regions, a second voltage reference of a second polarity to the first region, and a third voltage reference of the second polarity to the second electrode of the capacitor. The first and second voltage references bias the first MOS transistor so that the third voltage reference for erasing the single poly layer memory cell does not cause a junction breakdown of the first MOS transistor.