Chung Man Leung

US Patent:

6355524, Mar 12, 2002

Filed:

Aug 15, 2000

Appl. No.:

09/640139

Inventors:

Hsing Ti Tuan - Cupertino CA
Li-Chun Li - Los Gatos CA
Chung Wai Leung - Milpitas CA
Thomas Tong-Long Chang - Santa Clara CA

Assignee:

Mosel Vitelic, Inc. - Hsin Chu

International Classification:

H01L 21336

US Classification:

438257

Abstract:

In a nonvolatile memory, select gates are self-aligned spacers formed on sidewalls of floating/control gate stacks. The same mask ( ) is used to remove the select gate layer from over the source lines ( ), to etch trench insulation in the source line regions, and to dope the source lines. The memory can be formed in and over an isolated substrate region. The source lines can be doped at least partially before the trench insulation is etched, to prevent a short before the source lines and a region isolating the isolated substrate region from below. The memory can be erased by sectors, or alternatively a chip erase operation can be performed to erase all the cells in parallel. Peripheral transistor gates can be formed from the same layer as the select gates. The select gate spacers have extensions to which low resistance contacts can be made from overlying metal lines.

US Patent:

6566196, May 20, 2003

Filed:

May 15, 2002

Appl. No.:

10/146979

Inventors:

Barbara Haselden - Cupertino CA
Chia-Shun Hsiao - Cupertino CA
Chunchieh Huang - San Jose CA
Jin-Ho Kim - San Jose CA
Chung Wai Leung - Milpitas CA

Assignee:

Mosel Vitelic, Inc. - Hsin Chu

International Classification:

H01L 21336

US Classification:

438257, 438954

Abstract:

In a nonvolatile memory, a floating gate ( ) is covered with ONO ( ), and a control gate polysilicon layer ( ) is formed on the ONO. After the control gate is patterned, the control gate sidewalls are oxidized to form a protective layer ( ) of silicon dioxide. This oxide protects the control gate polysilicon during a subsequent etch of the silicon nitride portion ( ) of the ONO. Therefore, the silicon nitride can be removed with an isotropic etch. A potential damage to the substrate isolation dielectric ( ) is therefore reduced. Other embodiments are also provided.

US Patent:

6559055, May 6, 2003

Filed:

Apr 30, 2001

Appl. No.:

09/846123

Inventors:

Hsing Ti Tuan - Cupertino CA
Chung Wai Leung - Milpitas CA

Assignee:

Mosel Vitelic, Inc.

International Classification:

H01L 21336

US Classification:

438692, 438926

Abstract:

Circuit elements (e. g. transistor gates) formed over a semiconductor substrate are protected by adjacent dummy structures during mechanical or chemical mechanical polishing of an overlying dielectric.

US Patent:

6570215, May 27, 2003

Filed:

Jul 18, 2002

Appl. No.:

10/199157

Inventors:

Hsing T. Tuan - Cupertino CA
Vei-Han Chan - San Jose CA
Chung Wai Leung - Milpitas CA
Chia-Shun Hsiao - Hsin-Chu, TW

Assignee:

Mosel Vitelic, Inc. - Hsin Chu

International Classification:

H01L 2362

US Classification:

257315, 438257, 438258, 438259, 438266, 438267, 438296, 438315

Abstract:

In a nonvolatile memory, a floating gate includes a portion of a conductive layer ( ), and also includes conductive spacers ( ). The spacers increase the capacitive coupling between the floating gate and the control gate ( ).

US Patent:

6700143, Mar 2, 2004

Filed:

Jun 6, 2002

Appl. No.:

10/165741

Inventors:

Hsing Ti Tuan - Cupertino CA
Chung Wai Leung - Milpitas CA

Assignee:

Mosel Vitelic, Inc. - Hsin-Chu

International Classification:

H01L 31119

US Classification:

257288, 287296, 287750, 287758, 287752

Abstract:

Circuit elements (e. g. transistor gates) formed over a semiconductor substrate are protected by adjacent dummy structures during mechanical or chemical mechanical polishing of an overlying dielectric.

US Patent:

6815302, Nov 9, 2004

Filed:

Dec 21, 2001

Appl. No.:

10/028614

Inventors:

Alan Sangone Chen - Windermere FL
Yih-Feng Chyan - New Providence NJ
Chung Wai Leung - Milpitas CA
Yi Ma - Orlando FL
William John Nagy - Orlando FL

Assignee:

Agere Systems Inc. - Allentown PA

International Classification:

H01L 218228

US Classification:

438323, 438324, 438343, 438365

Abstract:

The present invention provides a method of manufacturing a bipolar transistor. The method may comprise forming a collector in a semiconductor wafer substrate, forming a base in the collector, implanting an oxide region within said collector and over the base, and forming an emitter over the substrate such that the oxide region is located between the emitter and the base.

US Patent:

6815760, Nov 9, 2004

Filed:

Jul 22, 2002

Appl. No.:

10/200443

Inventors:

Chung Wai Leung - Milpitas CA
Chia-Shun Hsiao - Cupertino CA
Vei-Han Chan - San Jose CA

Assignee:

Mosel Vitelic, Inc. - Hsin-Chu

International Classification:

H01L 29788

US Classification:

257316

Abstract:

To fabricate a semiconductor memory, one or more pairs of first structures are formed over a semiconductor substrate. Each first structure comprises (a) a plurality of floating gates of memory cells and (b) a first conductive line providing control gates for the memory cells. The control gates overlie the floating gates. Each pair of the first structures corresponds to a plurality of doped regions each of which provides a source/drain region to a memory cell having the floating and control gates in one or the structure and a source/drain region to a memory cell having floating and control gates in the other one of the structures. For each pair, a second conductive line is formed whose bottom surface extends between the two structures and physically contacts the corresponding first doped regions. In some embodiments, the first doped regions are separated by insulation trenches. The second conductive line may form a conductive plug at least partially filling the region between the two first structures.

US Patent:

6821847, Nov 23, 2004

Filed:

Oct 2, 2001

Appl. No.:

09/969841

Inventors:

Chung Wai Leung - Milpitas CA
Chia-Shun Hsiao - Cupertino CA
Vei-Han Chan - San Jose CA

Assignee:

Mosel Vitelic, Inc. - Hsin Chu

International Classification:

H01L 218247

US Classification:

438257

Abstract:

To fabricate a semiconductor memory, one or more pairs of first structures are formed over a semiconductor substrate. Each first structure comprises (a) a plurality of floating gates of memory cells and (b) a first conductive line providing control gates for the memory cells. The control gates overlie the floating gates. Each pair of the first structures corresponds to a plurality of doped regions each of which provides a source/drain region to a memory cell having the floating and control gates in one or the structure and a source/drain region to a memory cell having floating and control gates in the other one of the structures. For each pair, a second conductive line is formed whose bottom surface extends between the two structures and physically contacts the corresponding first doped regions. In some embodiments, the first doped regions are separated by insulation trenches. The second conductive line may form a conductive plug at least partially filling the region between the two first structures.