Cuong Viet Do

US Patent:

53496590, Sep 20, 1994

Filed:

Jan 23, 1992

Appl. No.:

7/824599

Inventors:

Cuong Do - San Jose CA
Ruey-Sing Wei - Fremont CA

Assignee:

Cadence Design Systems, Inc.

International Classification:

G06F 1560

US Classification:

395700

Abstract:

A system and method are described for decreasing the synthesis time required for realizing digital circuit net lists using library logic elements. The system consists of a logic processor working in concert with a cell library register, a hierarchical cell array memory, and a match register, for the purpose of hierarchically ordering, matching and eliminating equivalencies in the canonical forms of library cells. The method includes the reduction of all library elements to their canonical forms and the hierarchical ordering of the these canonicals based on the number of nodes contained in each element. Once ordered, the canonicals are mapped by logic elements having fewer nodes, beginning with the simplest of the canonical forms. Redundantly mapped logical elements are eliminated and the resulting reduced set is stored for subsequent use.