Daniel M Post

US Patent:

8321647, Nov 27, 2012

Filed:

Aug 20, 2009

Appl. No.:

12/545011

Inventors:

Vadim Khmelnitsky - Foster City CA, US
Nir Jacob Wakrat - Los Altos CA, US
Tahoma Toelkes - San Jose CA, US
Daniel Jeffrey Post - Campbell CA, US
Anthony Fai - Palo Alto CA, US

Assignee:

Apple Inc. - Cupertino CA

International Classification:

G06F 13/00
G06F 13/28

US Classification:

711170, 711154, 711E12002

Abstract:

Multipage preparation commands for non-volatile memory systems are disclosed. The multipage preparation commands supply data that can be used to prepare a non-volatile memory device for forthcoming multipage program operations. A host controller can use the commands ahead of a multipage program operation to optimize usage of a multipage program command. The non-volatile memory device can use the commands to configure the non-volatile memory in preparation for a subsequent operation, such as changing a command order or using the most optimized command set for the subsequent operation.

US Patent:

8370603, Feb 5, 2013

Filed:

Nov 6, 2009

Appl. No.:

12/614369

Inventors:

Tahoma Toelkes - San Jose CA, US
Nir Jacob Wakrat - Los Altos CA, US
Kenneth L. Herman - San Jose CA, US
Barry Corlett - Brisbane CA, US
Vadim Khmelnitsky - Foster City CA, US
Anthony Fai - Palo Alto CA, US
Daniel Jeffrey Post - Campbell CA, US
Hsiao Thio - San Jose CA, US

Assignee:

Apple Inc. - Cupertino CA

International Classification:

G06F 12/00
G06F 13/00
G06F 13/28
G06F 9/34
G06F 9/26

US Classification:

711202, 711103

Abstract:

The disclosed architecture uses address mapping to map a block address on a host interface to an internal block address of a non-volatile memory (NVM) device. The block address is mapped to an internal chip select for selecting a Concurrently Addressable Unit (CAU) identified by the block address. The disclosed architecture supports generic NVM commands for read, write, erase and get status operations. The architecture also supports an extended command set for supporting read and write operations that leverage a multiple CAU architecture.

US Patent:

8456938, Jun 4, 2013

Filed:

Mar 14, 2012

Appl. No.:

13/419567

Inventors:

Matthew J. Byom - San Jose CA, US
Daniel J. Post - Campbell CA, US
Vadim Khmelnitsky - Foster City CA, US

Assignee:

Apple Inc. - Cupertino CA

International Classification:

G11C 7/00

US Classification:

365222, 36518525

Abstract:

Systems and methods are disclosed for managing a non-volatile memory (“NVM”), such as a flash memory. To prevent data errors due to leakage effects, the NVM may be refreshed. For example, a reserved portion of the NVM may be selected, and a predetermined pattern can be stored into the reserved portion. The reserved portion can then be monitored for storage deterioration over time. After determining that storage deterioration of the reserved portion has occurred, the NVM can be refreshed. In some embodiments, a controller can attempt to distinguish data errors due to leakage effects from data errors due to disturb issues.

US Patent:

8458133, Jun 4, 2013

Filed:

Jan 24, 2011

Appl. No.:

13/012005

Inventors:

Nir J. Wakrat - Los Altos CA, US
Daniel J. Post - Cupertino CA, US
Dominic Giampaolo - Mountain View CA, US

Assignee:

Apple Inc. - Cupertino CA

International Classification:

G06F 17/30
G06F 17/00

US Classification:

707648, 707649, 707645, 711162

Abstract:

Systems and methods for coordinating sync points between a non-volatile memory (“NVM”) and a file system are provided. In some embodiments, a file system can issue one or more commands to control circuitry of a NVM, which can indicate whether a transaction is journaled or non-journaled. This way, the control circuitry can maintain a list of journaled transactions and corresponding LBA(s). By keeping track of journaled transactions, the control circuitry can ensure that sync points are not prematurely erased during a garbage collection process. In addition, upon detecting device failure events, the control circuitry can roll back to sync points corresponding to one or more journaled transactions.

US Patent:

8495332, Jul 23, 2013

Filed:

Jul 24, 2009

Appl. No.:

12/509240

Inventors:

Nir Jacob Wakrat - Los Altos CA, US
Vadim Khmelnitsky - Foster City CA, US
Daniel Jeffrey Post - Campbell CA, US

Assignee:

Apple Inc. - Cupertino CA

International Classification:

G06F 13/00

US Classification:

711173, 711103, 711135, 711202, 711206

Abstract:

A controller, techniques, systems, and devices for optimizing throughput of read operations in flash memory are disclosed. Various optimizations of throughput for read operations can be performed using a controller. In some implementations, read operations for a multi-die flash memory device or system can be optimized to perform a read request with a highest priority (e. g. , an earliest received read request) as soon as the read request is ready. In some implementations, the controller can enable optimized reading from multiple flash memory dies by monitoring a read/busy state for each die and switching between dies when a higher priority read operation is ready to begin.

US Patent:

8521948, Aug 27, 2013

Filed:

Jan 3, 2011

Appl. No.:

12/983715

Inventors:

Daniel J. Post - Cupertino CA, US
Nir J. Wakrat - Los Altos CA, US

Assignee:

Apple Inc. - Cupertino CA

International Classification:

G06F 12/00

US Classification:

711103

Abstract:

Systems and methods are disclosed for handling dynamic and static data for a system having non-volatile memory (“NVM”). By determining whether data being written to the NVM is dynamic or not, a NVM interface of a system can determine where to initially place the data on the NVM (e. g. , place the data on either a dynamic stream block or a static stream block). Moreover, this information can allow the NVM interface to improve the efficiencies of both garbage collection (“GC”) and wear leveling.

US Patent:

8595414, Nov 26, 2013

Filed:

Sep 30, 2010

Appl. No.:

12/895039

Inventors:

Daniel J. Post - Cupertino CA, US
Nir J. Wakrat - Los Altos CA, US
Vadim Khmelnitsky - Foster City CA, US

Assignee:

Apple Inc. - Cupertino CA

International Classification:

G06F 12/02

US Classification:

711103, 711102, 711206, 711E12008, 711E12078, 710308

Abstract:

Systems and methods are disclosed for selectively combining commands for a system having non-volatile memory (“NVM”). In some embodiments, a command dispatcher of a system can receive multiple commands to access a NVM for a period of time. After receiving the multiple commands, the command dispatcher can determine a set of commands that are naturally combinable. In some embodiments, the command dispatcher can select commands that are fairly distributed across different chip enables (“CEs”) and/or buses. After selecting the set of commands, the command dispatcher can combine the set of commands into a multi-access command. Finally, the command dispatcher can dispatch the multi-access command to the NVM.

US Patent:

8645615, Feb 4, 2014

Filed:

Dec 9, 2010

Appl. No.:

12/964423

Inventors:

Daniel J. Post - Cupertino CA, US
Nir J. Wakrat - Los Altos CA, US

Assignee:

Apple Inc. - Cupertino CA

International Classification:

G06F 12/00

US Classification:

711103

Abstract:

This can relate to handling a non-volatile memory (“NVM”) operating at a substantially full memory. The non-volatile memory can report its physical capacity to an NVM driver. The NVM driver can scale-up the physical capacity a particular number of times to generate a “scaled physical capacity,” which is then reported to the file system. Because the scaled physical capacity is greater than the NVM's actual physical capacity, the file system allocates a logical space to the NVM that is substantially greater than the NVM's capacity. This can cause less crowding of the logical block addresses within the logical space, thus making it easier for the file system to operate and improving system performance. A commitment budget can also be reported to the file system that corresponds to the NVM's physical capacity, and which can define the amount of data the file system can commit for storage in the NVM.