Daniel Anthony Post

US Patent:

8164967, Apr 24, 2012

Filed:

Mar 24, 2010

Appl. No.:

12/730617

Inventors:

Matthew Byom - Campbell CA, US
Daniel J. Post - Campbell CA, US
Vadim Khmelnitsky - Foster City CA, US

Assignee:

Apple Inc. - Cupertino CA

International Classification:

G11C 7/00

US Classification:

365222, 36518525

Abstract:

Systems and methods are disclosed for managing a non-volatile memory (“NVM”), such as a flash memory. To prevent data errors due to leakage effects, the NVM may be refreshed. For example, a reserved portion of the NVM may be selected, and a predetermined pattern can be stored into the reserved portion. The reserved portion can then be monitored for storage deterioration over time. After determining that storage deterioration of the reserved portion has occurred, the NVM can be refreshed. In some embodiments, a controller can attempt to distinguish data errors due to leakage effects from data errors due to disturb issues.

US Patent:

8321647, Nov 27, 2012

Filed:

Aug 20, 2009

Appl. No.:

12/545011

Inventors:

Vadim Khmelnitsky - Foster City CA, US
Nir Jacob Wakrat - Los Altos CA, US
Tahoma Toelkes - San Jose CA, US
Daniel Jeffrey Post - Campbell CA, US
Anthony Fai - Palo Alto CA, US

Assignee:

Apple Inc. - Cupertino CA

International Classification:

G06F 13/00
G06F 13/28

US Classification:

711170, 711154, 711E12002

Abstract:

Multipage preparation commands for non-volatile memory systems are disclosed. The multipage preparation commands supply data that can be used to prepare a non-volatile memory device for forthcoming multipage program operations. A host controller can use the commands ahead of a multipage program operation to optimize usage of a multipage program command. The non-volatile memory device can use the commands to configure the non-volatile memory in preparation for a subsequent operation, such as changing a command order or using the most optimized command set for the subsequent operation.

US Patent:

8341500, Dec 25, 2012

Filed:

Aug 31, 2010

Appl. No.:

12/872884

Inventors:

Matthew Byom - Campbell CA, US
Daniel J. Post - Cupertino CA, US
Vadim Khmelnitsky - Foster City CA, US
Nir J. Wakrat - Los Altos CA, US

Assignee:

Apple Inc. - Cupertino CA

International Classification:

G11C 29/00

US Classification:

714773, 714763, 36518533, 375286

Abstract:

Systems, apparatuses, and methods are provided for detecting corrupted data for a system having non-volatile memory, such as NAND Flash memory. In some embodiments, a non-volatile memory (“NVM”) package is provided, which can include a NVM controller and one or more NVM dies. Each NVM die can include one or more blocks, where each block can further include an array of memory cells. One or more of these memory cells can be configured as “multi-level cells” (“MLCs”). In some embodiments, in order to avoid transmitting data obtained from an improperly programmed page of a MLC, a NVM controller can be configured to detect if data obtained from the page is in fact data stored in a different page.

US Patent:

8356137, Jan 15, 2013

Filed:

Feb 26, 2010

Appl. No.:

12/713529

Inventors:

Daniel J. Post - Campbell CA, US
Matthew Byom - Campbell CA, US
Vadim Khmelnitsky - Foster City CA, US
Nir J. Wakrat - Los Altos CA, US
Kenneth Herman - San Jose CA, US

Assignee:

Apple Inc. - Cupertino CA

International Classification:

G06F 12/06
G11C 20/00

US Classification:

711103, 711158, 714763, 714768, 714773

Abstract:

Systems and methods are disclosed for partitioning data for storage in a non-volatile memory (“NVM”), such as flash memory. In some embodiments, a priority may be assigned to data being stored, and the data may be logically partitioned based on the priority. For example, a file system may identify a logical address within a first predetermined range for higher priority data and within a second predetermined range for lower priority data, such using a union file system. Using the logical address, a NVM driver can determine the priority of data being stored and can process (e. g. , encode) the data based on the priority. The NVM driver can store an identifier in the NVM along with the data, and the identifier can indicate the processing techniques used on the associated data.

US Patent:

8370603, Feb 5, 2013

Filed:

Nov 6, 2009

Appl. No.:

12/614369

Inventors:

Tahoma Toelkes - San Jose CA, US
Nir Jacob Wakrat - Los Altos CA, US
Kenneth L. Herman - San Jose CA, US
Barry Corlett - Brisbane CA, US
Vadim Khmelnitsky - Foster City CA, US
Anthony Fai - Palo Alto CA, US
Daniel Jeffrey Post - Campbell CA, US
Hsiao Thio - San Jose CA, US

Assignee:

Apple Inc. - Cupertino CA

International Classification:

G06F 12/00
G06F 13/00
G06F 13/28
G06F 9/34
G06F 9/26

US Classification:

711202, 711103

Abstract:

The disclosed architecture uses address mapping to map a block address on a host interface to an internal block address of a non-volatile memory (NVM) device. The block address is mapped to an internal chip select for selecting a Concurrently Addressable Unit (CAU) identified by the block address. The disclosed architecture supports generic NVM commands for read, write, erase and get status operations. The architecture also supports an extended command set for supporting read and write operations that leverage a multiple CAU architecture.

US Patent:

8411519, Apr 2, 2013

Filed:

Jul 23, 2010

Appl. No.:

12/842477

Inventors:

Matthew Byom - Campbell CA, US
Daniel J. Post - Campbell CA, US
Vadim Khmelnitsky - Foster City CA, US

Assignee:

Apple Inc. - Cupertino CA

International Classification:

G11C 29/00

US Classification:

365200, 36523003, 714 42, 714718

Abstract:

Systems and methods are provided for selectively retiring blocks based on refresh events of those blocks. In addition to refresh events, other criteria may be applied in making a decision whether to retire a block. By applying the criteria, the system is able to selectively retire blocks that may otherwise continue to be refreshed.

US Patent:

8438453, May 7, 2013

Filed:

Aug 7, 2009

Appl. No.:

12/538053

Inventors:

Daniel Jeffrey Post - Campbell CA, US
Nir Jacob Wakrat - Los Altos CA, US
Vadim Khmelnitsky - Foster City CA, US

Assignee:

Apple Inc. - Cupertino CA

International Classification:

G11C 29/00

US Classification:

714763

Abstract:

In a memory system, a host controller is coupled to a non-volatile memory (NVM) package (e. g. , NAND device). The host controller sends a read command to the NVM package requesting a low latency read operation. Responsive to the read command, a controller in the NVM package retrieves the data and sends the data to an ECC engine for correcting. Following the read command, the host controller sends a read status request command to the controller in the NVM package. Responsive to the read status request, the controller sends a status report to the host controller indicating that some or all of the data is available for transfer to the host controller. Responsive to the report, the host controller transfers the data. An underrun status can be determined to indicate that uncorrected data had been transferred to the host controller.

US Patent:

8456938, Jun 4, 2013

Filed:

Mar 14, 2012

Appl. No.:

13/419567

Inventors:

Matthew J. Byom - San Jose CA, US
Daniel J. Post - Campbell CA, US
Vadim Khmelnitsky - Foster City CA, US

Assignee:

Apple Inc. - Cupertino CA

International Classification:

G11C 7/00

US Classification:

365222, 36518525

Abstract:

Systems and methods are disclosed for managing a non-volatile memory (“NVM”), such as a flash memory. To prevent data errors due to leakage effects, the NVM may be refreshed. For example, a reserved portion of the NVM may be selected, and a predetermined pattern can be stored into the reserved portion. The reserved portion can then be monitored for storage deterioration over time. After determining that storage deterioration of the reserved portion has occurred, the NVM can be refreshed. In some embodiments, a controller can attempt to distinguish data errors due to leakage effects from data errors due to disturb issues.