Daniel E Post

US Patent:

8321647, Nov 27, 2012

Filed:

Aug 20, 2009

Appl. No.:

12/545011

Inventors:

Vadim Khmelnitsky - Foster City CA, US
Nir Jacob Wakrat - Los Altos CA, US
Tahoma Toelkes - San Jose CA, US
Daniel Jeffrey Post - Campbell CA, US
Anthony Fai - Palo Alto CA, US

Assignee:

Apple Inc. - Cupertino CA

International Classification:

G06F 13/00
G06F 13/28

US Classification:

711170, 711154, 711E12002

Abstract:

Multipage preparation commands for non-volatile memory systems are disclosed. The multipage preparation commands supply data that can be used to prepare a non-volatile memory device for forthcoming multipage program operations. A host controller can use the commands ahead of a multipage program operation to optimize usage of a multipage program command. The non-volatile memory device can use the commands to configure the non-volatile memory in preparation for a subsequent operation, such as changing a command order or using the most optimized command set for the subsequent operation.

US Patent:

20130073789, Mar 21, 2013

Filed:

Sep 16, 2011

Appl. No.:

13/235019

Inventors:

Vadim Khmelnitsky - Foster City CA, US
Daniel J. Post - Cupertino CA, US
Nir Jacob Wakrat - Los Altos CA, US
Matthew J. Byom - San Jose CA, US
Kenneth Herman - San Jose CA, US
Alexander Sanks - Menlo Park CA, US

Assignee:

APPLE INC. - Cupertino CA

International Classification:

G06F 12/02

US Classification:

711103, 711E12008

Abstract:

Systems and methods are disclosed for configuring a non-volatile memory (“NVM”). In some embodiments, each block of the NVM can include a block table-of-contents (“TOC”), which can be encoded (e.g., run-length encoded) and dynamically-sized. Thus, as user data is being programmed to a block, the size of a block TOC can be concurrently recalculated and increased only if necessary. In some embodiments, the NVM interface can use a weave sequence stored in the context information and at least one weave sequence associated with each page of a block to determine whether to replay across the pages of the block after system boot-up.

US Patent:

20220247789, Aug 4, 2022

Filed:

Jan 29, 2021

Appl. No.:

17/163084

Inventors:

- San Francisco CA, US
Sam Sanjabi - Toronto, CA
Royal Chan - Alameda CA, US
Vincent Voong - San Francisco CA, US
Daniel Jeffrey Post - Pacifica CA, US
Cedric Beust - Sunnyvale CA, US

International Classification:

H04L 29/06
G06F 3/0482
G06F 3/0484

Abstract:

An identity provider (“IdP”) system maintains a framework of authentication methods and security targets that enables flexible authentication policy authoring and analysis of authentication performed by users of an organization. The IdP system generates authentication method profiles that include authentication factors and attributes, which may be further classified as required or optional. The IdP system also generates security target profiles that indicate security requirements needed to satisfy the corresponding security targets. The IdP system uses the generated profiles to determine relationships between authentication methods and security targets (e.g., a list of authentication methods that satisfy a given security target). Using these relationships, the IdP system may enable users to author policies and analyze how users' authentication behaviors comply with security targets.

US Patent:

20200233452, Jul 23, 2020

Filed:

Dec 17, 2019

Appl. No.:

16/718135

Inventors:

- San Francisco CA, US
Peter Miles Twiss - San Mateo CA, US
Daniel Jeffrey Post - Pacifica CA, US
Anthony Ambuehl - El Cerrito CA, US
Michael J. Strasser - San Francisco CA, US
Eric Strasser - San Francisco CA, US

International Classification:

G06F 1/16
A61B 5/00
H02J 7/00
G08B 5/36
G06F 3/14
G08C 17/02
G04G 21/02
G06F 3/01
G06K 9/00
G08B 21/02
G01P 15/00
G06F 3/147
A61B 5/0402
A61B 5/0205
A61B 5/11
G06F 3/0346
A61B 5/01
G06F 21/44

Abstract:

The disclosure discloses a wearable computing device (WCD) that would selectively and automatically activate a transceiver of the WCD for data transmission based on sensor data obtained from a sensor module of the \VCD. In some example, the sensor module may convert the physical movements of the WCD into sensor data. Then, a processor module of the WCD compares the sensor data to a predetern lined pattern pre-stored in the memory. If the sensor data matches the predetermined pattern, the processor module activates the transceiver to receive/transmit data packets. If the sensor data does not match the predetermined pattern, the process goes back to the beginning, where the processor module monitors the movement of the WCD through the sensors.

US Patent:

20180120892, May 3, 2018

Filed:

Dec 27, 2017

Appl. No.:

15/854783

Inventors:

- San Francisco CA, US
Peter Miles Twiss - San Mateo CA, US
Daniel Jeffrey Post - Pacifica CA, US
Anthony Ambuehl - El Cerrito CA, US
Michael J. Strasser - San Francisco CA, US
Eric Strasser - San Francisco CA, US

Assignee:

Motiv Inc. - San Francisco CA

International Classification:

G06F 1/16
H02J 7/00
A61B 5/00
G08C 17/02
G08B 21/02
G08B 5/36
G06K 9/00
G06F 3/14
G06F 3/01
G04G 21/02
G01P 15/00

Abstract:

The disclosure discloses a wearable computing device (WCD) that would selectively and automatically activate a transceiver of the WCD for data transmission based on sensor data obtained from a sensor module of the WCD. In some example, the sensor module may convert the physical movements of the WCD into sensor data. Then, a processor module of the WCD compares the sensor data to a predetermined pattern pre-stored in the memory. If the sensor data matches the predetermined pattern, the processor module activates the transceiver to receive/transmit data packets. If the sensor data does not match the predetermined pattern, the process goes back to the beginning, where the processor module monitors the movement of the WCD through the sensors.

US Patent:

20160267470, Sep 15, 2016

Filed:

May 23, 2016

Appl. No.:

15/161891

Inventors:

- San Francisco CA, US
Daniel Jeffrey Post - San Mateo CA, US
Dominique Gilbert Toppani - San Francisco CA, US
Alex Sutton - San Francisco CA, US

International Classification:

G06Q 20/34
H04L 29/06
G06K 7/08

Abstract:

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for modulating card information between a card reader and a user device. One of the methods includes receiving, from a read head of the card reader, card information associated with a card. The card information is encoded in a first format to be sent to the user device at a first data rate. The card information is encoded in a second format to be sent to the user device at a second data rate lower than the first data rate. The card information is sent to the user device encoded in the first format and the second format.

US Patent:

20160092110, Mar 31, 2016

Filed:

Dec 8, 2015

Appl. No.:

14/962339

Inventors:

- Cupertino CA, US
Daniel J. Post - Pacifica CA, US
Nir Jacob Wakrat - Los Altos CA, US
Matthew J. Byom - San Jose CA, US
Kenneth L. Herman - San Jose CA, US
Alexander C. Sanks - Menlo Park CA, US

International Classification:

G06F 3/06

Abstract:

Systems and methods are disclosed for configuring a non-volatile memory (“NVM”). In some embodiments, each block of the NVM can include a block table-of-contents (“TOC”), which can be encoded (e.g., run-length encoded) and dynamically-sized. Thus, as user data is being programmed to a block, the size of a block TOC can be concurrently recalculated and increased only if necessary. In some embodiments, the NVM interface can use a weave sequence stored in the context information and at least one weave sequence associated with each page of a block to determine whether to replay across the pages of the block after system boot-up.

US Patent:

20150301760, Oct 22, 2015

Filed:

Jun 29, 2015

Appl. No.:

14/754468

Inventors:

- Cupertino CA, US
Daniel J. Post - Pacifica CA, US

International Classification:

G06F 3/06
G06F 11/10

Abstract:

Systems and methods are disclosed for correction of block errors for a system having non-volatile memory (“NVM”). In particular, the system can store a parity page per page-modulo, where a pre-determined number of pages of a block or a band of the NVM may be allocated as page-modulo XOR (“PMX”) parity pages. This can be a space efficient approach for recovering from single-block data errors such as, for example, single-page uncorrectable error-correcting codes (“uECCs”) and/or errors caused by word line shorts.