David A Ferris

US Patent:

46971033, Sep 29, 1987

Filed:

Mar 10, 1986

Appl. No.:

6/838519

Inventors:

David A. Ferris - West Buxton ME
Daniel J. DeSimone - Buxton ME

Assignee:

Quadic Systems, Inc. - South Portland ME

International Classification:

H03K 19088
H03K 1716
H03K 1900
H03K 326

US Classification:

307456

Abstract:

A multi-terminal transistor circuit structure is described for TTL applications including current sinking and "pull-down" transistor circuit elements. A transistor pair is coupled with the emitter of the second transistor coupled to the base of the first transistor. The collector and emitter of the first transistor provide first and second terminals and the bases of the transistor pair provide independent third and fourth terminals or current controlled inputs. The new circuit structure is incorporated in a tranistor transistor logic (TTL) output buffer circuit and provides first and second pull-down transistor elements having the emitter of the second transistor coupled to the base of the first pull-down transistor. An independent base drive is coupled to the base of the second pull-down transistor element. The second stage pull-down transistor element introduces full square law enhancement of. beta. sup.

US Patent:

46617272, Apr 28, 1987

Filed:

Jul 19, 1984

Appl. No.:

6/632433

Inventors:

David A. Ferris - West Buxton ME
Richard J. Caswell - Swindon, GB2

Assignee:

Fairchild Semiconductor Corporation - Palo Alto CA

International Classification:

H03K 19013
H03K 19088
H03K 1704
H03K 1760

US Classification:

307456

Abstract:

A multiple phase-splitter TTL tristate output circuit having a feedback diode coupled between the signal output and the collector of a first phase-splitter transistor to accelerate sinking of current from the output to low potential during transition of binary signals at the output from high to low potential. An independent base drive is coupled to the base of the first phase-splitter transistor independent from any base drive coupled to the other phase-splitter transistor or transistors. Current hogging of the base drive current to the first phase-splitter transistor by the other phase-splitter transistors is thereby prevented. The first phase-splitter transistor which is coupled in the feedback circuit with the accelerating feedback diode to the base of the pulldown transistor element can therefore maintain the high current sinking mode through the pulldown transistor element with gain step-up proportional to. beta. sup. 2 when the output is at the high voltage level.

US Patent:

43341578, Jun 8, 1982

Filed:

Feb 22, 1980

Appl. No.:

6/123717

Inventors:

David A. Ferris - West Buxton ME

Assignee:

Fairchild Camera and Instrument Corp. - Mountain View CA

International Classification:

H03K 3288
H03K 1700

US Classification:

307291

Abstract:

A data latch of the kind having at least two operative modes, a transmitting or transparent mode or condition for transmitting data signals through the latch, and a latching mode or condition for latching and temporary storage by feedback of data signals in the latch. According to the invention there is provided in the data latch a pregate for pregating feedback signals in the latch. The pregate is adapted and coupled to provide positive feedback data signals for reinforcing previously entered data in the latching mode, and gating signals for passing input data in the transmitting mode.

US Patent:

43119271, Jan 19, 1982

Filed:

Jul 18, 1979

Appl. No.:

6/058674

Inventors:

David A. Ferris - West Buxton ME

Assignee:

Fairchild Camera & Instrument Corp. - Mountain View CA

International Classification:

H03K 19088

US Classification:

307473

Abstract:

A transistor logic tristate output gate or device is provided with active or passive element arrangements coupled between the enable gate on the one hand and the base of the pull down element transistor on the other hand. This coupling affords a low impedance route to ground or low potential from the base of the pull down element when the enable gate is at low potential and the output device is in the high impedance third state. Miller feedback current at the base of the pull down element transistor is thereby diverted to ground. The coupling arrangement affords high impedance to current flow in the opposite direction thereby blocking current flow from the enable gate when the enable gate is at high potential. For active discharge of Miller current three transistors are provided in a double inversion series coupling between the enable gate and pull down element. Alternately a multiple emitter junction transistor is used.

US Patent:

45815500, Apr 8, 1986

Filed:

Mar 6, 1984

Appl. No.:

6/586671

Inventors:

David A. Ferris - West Buxton ME
Benny Chang - South Portland ME

Assignee:

Fairchild Camera & Instrument Corporation - Cupertino CA

International Classification:

H03K 19013
H03K 19088
H03K 19003

US Classification:

307473

Abstract:

An improved TTL tristate device with reduced output capacitance incorporates an active discharge sequence of three elements including first and second active transistor elements (Q8, Q7) in an inversion coupling and a third passive element comprising a passive diode cluster (D3, D4, D5) coupled between the base of the second transistor element (Q7) and the enable gate. The passive diode cluster is operatively arranged for delivering base drive current to the base of the second transistor (Q7) when the enable gate (A) is at high potential for operation of the output device in the bistate mode. The passive diode cluster also operatively diverts base drive current away from the base of the second transistor (Q7) when the enable gate (A) is at low potential for operation of the output device in the high impedance third state with reduced output capacitance. The first transistor element (Q8) of the active discharge sequence coupled to the base of the pull-down transistor element (Q4) follows in phase at its collector the potential maintained by the enable gate (A). It actively conducts, discharges and diverts capacitive feedback Miller current from the base of the pull-down transistor element (Q4) when the enable gate is at low potential, and presents a high impedance to current in the direction of the base of the pull-down transistor element (Q4) when the enable gate is at high potential.