David M Fong

US Patent:

20050275427, Dec 15, 2005

Filed:

Aug 11, 2004

Appl. No.:

10/916232

Inventors:

Man Wang - Sunnyvale CA, US
Guy Schlacter - Buffalo Grove IL, US
David Fong - Cupertino CA, US
Jianguo Wang - Cupertino CA, US
Jack Peng - San Jose CA, US

International Classification:

H03K019/177

US Classification:

326041000

Abstract:

The embodiments of the present invention relate to the general area of the Field Programmable Gate Arrays, and, in particular to the architecture and the structure of the building blocks of the Field Programmable Gate Arrays. The proposed logic units, as separate units or cluster of units, which are mainly comprised of look-up tables, multiplexers, and a latch, implement functions such as addition, subtraction, multiplication, and can perform as shift registers, finite state machines, multiplexers, accumulators, counters, multi-level random logic, and look-up tables, among other functions. Having two outputs, the embodiments of the logic unit can operate in split-mode and perform two separate logic and/or arithmetic functions at the same time. Clusters of the proposed logic units, which utilize local interconnections instead of traditional routing channels, add to efficiency, speed, and reduce required real estate.

US Patent:

D2500728, Oct 31, 1978

Filed:

Nov 26, 1976

Appl. No.:

5/745348

Inventors:

David G. Fong - San Francisco CA

International Classification:

D0601

US Classification:

D 6 56

US Patent:

20220393777, Dec 8, 2022

Filed:

Aug 15, 2022

Appl. No.:

17/888267

Inventors:

- San Diego CA, US
Giacomo RINALDI - San Diego CA, US
Matheus TREVISAN MOREIRA - San Diego CA, US
Matthew PRYOR - San Diego CA, US
David FONG - San Diego CA, US

International Classification:

H04B 17/15
H04B 17/29

Abstract:

This application discloses circuits and apparatus configured to measure performance of asynchronous circuits by injecting data in to inputs of asynchronous circuits and consuming data from the outputs without interfering in the functionality of the asynchronous circuits. This application also discloses systems and methods for assessing the performance of asynchronous channels and/or IP blocks by providing an unambiguous performance value which can be used for performance analysis and comparison.

US Patent:

20230075698, Mar 9, 2023

Filed:

Sep 6, 2022

Appl. No.:

17/903832

Inventors:

- San Diego CA, US
Giacomo RINALDI - San Diego CA, US
Matheus TREVISAN MOREIRA - San Diego CA, US
Matthew PRYOR - San Diego CA, US
David FONG - San Diego CA, US

International Classification:

H04L 7/00
H04L 41/06
H04L 47/24
H04L 49/90
H04L 49/101
H04L 49/00
H04L 49/25

Abstract:

Systems and methods for providing input and output ports to connect to channels are provided. Input and output ports are the basic building blocks to create more complex data routing IP blocks. By aggregating these modular ports in different ways, different implementations of crossbar or Network on Chip (NoC) can be implemented, allowing flexible routing structure while maintaining all the benefits of channels such as robustness against delay variation, data compression and simplified timing assumptions.

US Patent:

20200336284, Oct 22, 2020

Filed:

Jul 2, 2020

Appl. No.:

16/920203

Inventors:

- San Diego CA, US
Giacomo RINALDI - San Diego CA, US
Matheus TREVISAN MOREIRA - San Diego CA, US
Matthew PRYOR - San Diego CA, US
David FONG - San Diego CA, US

International Classification:

H04L 7/00
H04L 12/24
H04L 12/851
H04L 12/861
H04L 12/933
H04L 12/935
H04L 12/947

Abstract:

Systems and methods for providing input and output ports to connect to channels are provided. Input and output ports are the basic building blocks to create more complex data routing IP blocks. By aggregating these modular ports in different ways, different implementations of crossbar or Network on Chip (NoC) can be implemented, allowing flexible routing structure while maintaining all the benefits of channels such as robustness against delay variation, data compression and simplified timing assumptions.

US Patent:

20200259572, Aug 13, 2020

Filed:

Apr 27, 2020

Appl. No.:

16/859621

Inventors:

- San Diego CA, US
Giacomo RINALDI - San Diego CA, US
Matheus TREVISAN MOREIRA - San Diego CA, US
Matthew PRYOR - San Diego CA, US
David FONG - San Diego CA, US

International Classification:

H04B 17/15
H04B 17/29

Abstract:

This application discloses circuits and apparatus configured to measure performance of asynchronous circuits by injecting data in to inputs of asynchronous circuits and consuming data from the outputs without interfering in the functionality of the asynchronous circuits. This application also discloses systems and methods for assessing the performance of asynchronous channels and/or IP blocks by providing an unambiguous performance value which can be used for performance analysis and comparison.

US Patent:

20190379521, Dec 12, 2019

Filed:

Aug 21, 2019

Appl. No.:

16/547420

Inventors:

- San Diego CA, US
Giacomo Rinaldi - San Diego CA, US
Matheus Trevisan Moreira - San Diego CA, US
Matthew Pryor - San Diego CA, US
David Fong - San Diego CA, US

International Classification:

H04L 7/00
H04L 12/24
H04L 12/851
H04L 12/947
H04L 12/935
H04L 12/861
H04L 12/933

Abstract:

Systems and methods for providing input and output ports to connect to channels are provided. Input and output ports are the basic building blocks to create more complex data routing IP blocks. By aggregating these modular ports in different ways, different implementations of crossbar or Network on Chip (NoC) can be implemented, allowing flexible routing structure while maintaining all the benefits of channels such as robustness against delay variation, data compression and simplified timing assumptions.

US Patent:

20190179992, Jun 13, 2019

Filed:

Feb 4, 2019

Appl. No.:

16/266994

Inventors:

- San Diego CA, US
Giacomo RINALDI - San Diego CA, US
Matheus TREVISAN MOREIRA - San Diego CA, US
Matthew PRYOR - San Diego CA, US
David FONG - San Diego CA, US

International Classification:

G06F 17/50
H04L 12/801
G06F 13/42
H04L 12/40

Abstract:

Systems and methods for providing Chronos Channel interconnects in an ASIC are provided. Chronos Channels rely on a reduced set of timing assumptions and are robust against delay variations. Chronos Channels transmit data using delay insensitive (DI) codes and quasi-delay-insensitive (QDI) logic. Chronos Channels are insensitive to all wire and gate delay variations, but for those belonging to a few specific forking logic paths called isochronic forks. Chronos Channels use temporal compression in internal paths to reduce the overheads of QDI logic and efficiently transmit data. Chronos Channels are defined by a combination of a DI code, a temporal compression ratio and hardware.