David Charles Hart

US Patent:

8643067, Feb 4, 2014

Filed:

Sep 30, 2011

Appl. No.:

13/249529

Inventors:

Scott J. Alberhasky - Portland OR, US
David E. Hart - Cornelius OR, US
Sudarsan Uppili - Portland OR, US

Assignee:

Maxim Integrated Products, Inc. - San Jose CA

International Classification:

H01L 29/66

US Classification:

257263, 257302, 257328, 257E29262

Abstract:

Semiconductor devices are described that include a dual-gate configuration. In one or more implementations, the semiconductor devices include a substrate having a first surface and a second surface. The substrate includes a first and a second body region formed proximal to the first surface. Moreover, each body region includes a source region formed therein. The substrate further includes a drain region formed proximal to the second surface and an epitaxial region that is configured to function as a drift region between the drain region and the source regions. A dual-gate is formed over the first surface of the substrate. The dual-gate includes a first gate region and a second gate region that define a gap there between to reduce the gate to drain capacitance. A conductive layer may be formed over the first gate region and the second gate region to lower the effective resistance of the dual-gate.