David R Nguyen

US Patent:

6401167, Jun 4, 2002

Filed:

Oct 9, 1998

Appl. No.:

09/169206

Inventors:

Richard M. Barth - Palo Alto CA
Frederick A. Ware - Los Altos Hills CA
Donald C. Stark - Los Altos CA
Craig E. Hampel - San Jose CA
Paul G. Davis - San Jose CA
Abhijit M. Abhyankar - Sunnyvale CA
James A. Gasbarro - Mountain View CA
David Nguyen - San Jose CA

Assignee:

Rambus Incorporated - Los Altos CA

International Classification:

G06F 1200

US Classification:

711106, 36523003, 365233, 365222, 711154

Abstract:

A memory device includes an interconnect with mask pins and a memory core for storing data. A memory interface circuit is connected between the interconnect and the memory core. The memory interface circuit selectively processes write mask data from the mask pins or precharge instruction signals from the mask pins.

US Patent:

6590781, Jul 8, 2003

Filed:

Mar 26, 2001

Appl. No.:

09/817828

Inventors:

Ravindranath T. Kollipara - Fremont CA
David Nguyen - San Jose CA
Belgacem Haba - Cupertino CA

Assignee:

Rambus, Inc. - Los Altos CA

International Classification:

H05K 702

US Classification:

361760, 361789, 361684, 361790, 257684, 174250, 174267

Abstract:

An apparatus is provided, which includes a memory interface circuit, a clock signal generating circuit, and a plurality of memory circuits. The memory circuits are operatively coupled and arranged in an order on a plurality of memory modules, such that the memory module positioned at the beginning of the order is coupled to an output of the clock signal generating circuit and the memory interface circuit. The memory module that is positioned at the end of the order is unique in that it includes a clock signal terminating circuit connected to the last memory integrated circuit. With this configuration, a clock loop is formed by directly routing the clock signal from the output of the clock signal generating circuit through each of the memory modules in the order (without connecting to any of the intervening memory integrated circuits) to the memory integrated circuit positioned at the end of the order. Then, the clock signal is asserted on the previous memory modules by routing it back through the memory integrated circuits thereon, in reverse order to the memory integrated circuit positioned at the beginning of the order and from there to the memory interface circuit. To complete the clock loop, the clock signal is again asserted by routing it from the memory interface circuit back through the memory integrated circuits in order to the memory integrated circuit positioned at the end of the order.

US Patent:

6720643, Apr 13, 2004

Filed:

Feb 22, 2001

Appl. No.:

09/792788

Inventors:

Thomas F. Fox - Palo Alto CA
Sayeh Khalili - San Jose CA
Belgacem Haba - Cupertino CA
David Nguyen - San Jose CA
Richard Warmke - San Jose CA
Xingchao Yuan - Palo Alto CA

Assignee:

Rambus, Inc. - Los Altos CA

International Classification:

H01L 2302

US Classification:

257686, 257777, 257723

Abstract:

The semiconductor module is provided that includes a semiconductor housing and a plurality of integrated circuit dies positioned within the housing. The semiconductor module also includes a programmable memory device positioned within the housing and electrically coupled to the plurality of integrated circuit dies. The programmable memory device is programmable to identify the integrated circuit dies that meet a predetermined standard, such as an operating frequency requirement, or a core timing grade. Further, a method is provided for accessing a semiconductor module. The above mentioned housing is provided to enclose the plurality of integrated circuit dies and the programmable memory device. The integrated circuit dies of the plurality of integrated circuit dies that meet a predetermined standard are then identified. The programmable memory device is subsequently programmed to identify the selected integrated circuit dies.

US Patent:

6765800, Jul 20, 2004

Filed:

Apr 20, 2001

Appl. No.:

09/839642

Inventors:

Belgacem Haba - Cupertino CA
Richard E. Perego - San Jose CA
David Nguyen - San Jose CA
Ely Tsern - Los Altos CA
Craig E. Hampel - San Jose CA

Assignee:

Rambus Inc. - Los Altos CA

International Classification:

H05K 702

US Classification:

361760, 361775, 361675, 361803, 174 99 B, 174129 B, 174 71 B

Abstract:

Various module structures are disclosed which may be used to implement modules having 1 to N channels. Bus systems may be formed by the interconnection of such modules.

US Patent:

6808611, Oct 26, 2004

Filed:

Jun 27, 2002

Appl. No.:

10/187734

Inventors:

Chunman Yu - Sunnyvale CA
Brian Metzger - San Jose CA
David W. Nguyen - San Jose CA
Girish Dixit - San Jose CA

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

C25D 2100

US Classification:

205 81, 204400, 204434, 205775, 205787

Abstract:

Embodiments of the invention provide an electro-analytical method for determining the concentration of an organic additive in an acidic or basic metal plating bath using an organic chemical analyzer. The method includes preparing a supporting-electrolyte solution, preparing a testing solution including the supporting-electrolyte solution and a standard solution, measuring an electrochemical response of the supporting-electrolyte solution using the organic chemical analyzer, and implementing an electro-analytical technique to determine the concentration of the organic additive in the plating bath from the electrochemical response measurements. The method is performed for independently analyzing one organic additive component in a plating bath containing multi-component organic additives, regardless of knowledge of the concentration of other organic additives and with minimal interference among organic additives.

US Patent:

6868474, Mar 15, 2005

Filed:

Apr 22, 2002

Appl. No.:

10/128167

Inventors:

Richard M. Barth - Palo Alto CA, US
Frederick A. Ware - Los Altos Hills CA, US
Donald C. Stark - Los Altos CA, US
Craig E. Hampel - San Jose CA, US
Paul G. Davis - San Jose CA, US
Abhijit M. Abhyankar - Sunnyvale CA, US
James A. Gasbarro - Mountain View CA, US
David Nguyen - San Jose CA, US

Assignee:

Rambus Inc. - Los Altos CA

International Classification:

G06F012/00

US Classification:

711105, 711106, 711168, 365233, 36523003

Abstract:

A memory device includes an interconnect with mask pins and a memory core for storing data. A memory interface circuit is connected between the interconnect and the memory core. The memory interface circuit selectively processes write mask data from the mask pins or precharge instruction signals from the mask pins.

US Patent:

6898085, May 24, 2005

Filed:

Oct 30, 2003

Appl. No.:

10/695854

Inventors:

Belgacem Haba - Cupertino CA, US
Richard E. Perego - San Jose CA, US
David Nguyen - San Jose CA, US
Ely Tsern - Los Altos CA, US
Craig E. Hampel - San Jose CA, US

Assignee:

Rambus Inc. - Los Altos CA

International Classification:

H05K007/02
H05K007/06
H05K007/10

US Classification:

361760, 361720, 361748, 361775, 174 70 B, 174 88 B, 365 63

Abstract:

Various module structures are disclosed which may be used to implement modules having 1 to N channels. Bus systems may be formed by the interconnection of such modules.

US Patent:

6900958, May 31, 2005

Filed:

Jul 31, 2003

Appl. No.:

10/632434

Inventors:

Li Yi - Berkeley CA, US
Yanbin Song - Irvine CA, US
David A. Spaulding - San Juan Capistrano CA, US
Arafat M. Butt - Lake Forest CA, US
Robert J. McNab - San Jose CA, US
David D. Nguyen - Fountain Valley CA, US

Assignee:

Western Digital Technologies, Inc. - Lake Forest CA

International Classification:

G11B005/596

US Classification:

360 7702, 360 25

Abstract:

A method is disclosed for improving head position accuracy in a disk drive during track following of concentric data storage tracks through real-time identification of external vibration and monitoring of write-unsafe (WUS) occurrences. In the method, after a seek operation to a predetermined data storage track, the track is followed using a servo control loop having a nominal gain and responsive to a position error signal (PES). After waiting a vibration detection delay period, occurrences of the PES exceeding a WUS limit are counted generating a WUS limit exception count. Also, a property of a variance is determined from spectral power values generated from the PES during track following. If the WUS limit exception count exceeds a first threshold, and if the property of the variance exceeds a second threshold, the nominal gain is increased to a vibration gain within a frequency band, to attenuate the effect of external vibration.