David J Stanek

US Patent:

6373906, Apr 16, 2002

Filed:

Jan 24, 2001

Appl. No.:

09/768802

Inventors:

Roy Daron Cideciyan - Rueschlikon, CH
Jonathan Darrel Coker - Rochester MN
Evangelos S. Eleftheriou - Zurich, CH
Richard Leo Galbraith - Rochester MN
Allen Prescott Haar - Essex Junction VT
David James Stanek - Rochester MN

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H04L 2706

US Classification:

375341, 714769

Abstract:

Apparatus is provided for implementing high-speed and area efficient architectures for Viterbi detection of generalized partial response signals including two-way add/compare/select for improved channel speed. The two-way add/compare/select includes a two-way compare for comparing first and second state metric input values and a pair of two-way adds in parallel with the two-way compare for respectively adding the first and second state metric input values with a second input value. The second input value includes a time varying term or a constant term. The time varying terms are expressed as outputs Z of a partial matched filter or as outputs W of a matched filter. A multiplexer is coupled to the pair of two-way adds, the multiplexer receiving a selectable input controlled by the two-way compare. A pair of shifts coupled between the pair of two-way adds and the multiplexer receive a shift control input for providing metric bounding to avoid underflow. The two-way compare for comparing first and second state metric input values can include a hard shift for providing an add for the first state metric input value and then a compare between a resultant first state metric input value and the second state metric input value.

US Patent:

6377635, Apr 23, 2002

Filed:

Oct 26, 2000

Appl. No.:

09/697467

Inventors:

Roy Daron Cideciyan - Rueschlikon, CH
Jonathan Darrel Coker - Rochester MN
Evangelos S. Eleftheriou - Zurich, CH
Richard Leo Galbraith - Rochester MN
David James Stanek - Rochester MN

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03D 100

US Classification:

375341, 375291

Abstract:

Methods and apparatus are provided for implementing high-speed and area efficient architectures for Viterbi detection of generalized partial response signals using both partial matched filter and matched filter metrics. In the method of the invention, branch metric terms are transformed to shift all time varying terms and some constant terms after an add compare select (ACS) unit. The total number of non-zero constants on trellis branches is minimized. The shifted time varying terms and the shifted constant terms are added directly to state metric terms. The time varying terms are expressed as outputs Z of a partial matched filter or as outputs W of a matched filter. For a given generalized partial response target, the time-invariance property of the Viterbi detector enables identifying the minimum number of non-zero constants on trellis branches without resorting to heuristics. The time-invariance property holds for Viterbi detectors that process multiple samples per trellis-branch, thus allowing implementations at any desired speed.

US Patent:

6747829, Jun 8, 2004

Filed:

Jun 29, 2001

Appl. No.:

09/896465

Inventors:

David James Stanek - Rochester MN
Weldon Mark Hanson - Rochester MN

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G11B 509

US Classification:

360 53, 360 48, 360 51

Abstract:

An apparatus and method for transferring data between a read/write transducer coupled to a data channel and a data storage medium eliminates the necessity of a data sector block coding pad field. A data sector is received during a read operation. A disable signal associated with a last block of the data sector is generated. In response to the disable signal, data correction, such as parity correction, to the last block of the data sector is disabled. Data correction is enabled for application to blocks of the data sector other than the last block. Generating the disable signal involves identifying the last block of the data sector, which may be accomplished by detecting a change of state of a read gate input into the data channel or by use of a counter. The apparatus and method of the present invention may be embodied within a data channel of a data storing system, such as a direct access storage system.

US Patent:

6812867, Nov 2, 2004

Filed:

Jun 5, 2003

Appl. No.:

10/455696

Inventors:

Roy D Cideciyan - Rueschlikon, CH
Ajay Dholakia - Gattikon, CH
Evangelos S Eleftheriou - Zurich, CH
Richard L Galbraith - Rochester MN
Thomas Mittelholzer - Zurich, CH
Travis R Oenning - Rochester MN
David J Stanek - Rochester MN

Assignee:

International Business Machines Corp. - Armonk NY

International Classification:

H03M 700

US Classification:

341 59, 714800

Abstract:

Described is a modulation encoder having a finite state machine for converting input bits into output bits in which the number of alternating output bits is limited to j+1 where j is a predefined maximum number of transitions in the output bits, and in which the number of like output bits is limited to k+1 where k is a predefined maximum number of non-transitions in the output bits. The modulation encoder may be employed in encoding apparatus for converting an input bit stream into an output bit stream. Such apparatus may comprise partitioning logic for partitioning the input bit stream into a first group of bits and a second group of bits. A plurality of the aforementioned modulation encoders may be connected to the partitioning logic for converting the first group of bits into coded output bits. Combining logic may be connected to the or each modulation encoder and the partitioning logic for combining the coded output bits and the second group of bits to generate the output bit stream. Counterpart modulation decoders and decoding apparatus are also described.

US Patent:

6879629, Apr 12, 2005

Filed:

Mar 12, 2001

Appl. No.:

09/804094

Inventors:

Richard Leo Galbraith - Rochester MN, US
David James Stanek - Rochester MN, US

Assignee:

Hitachi Global Storage Technologies Netherlands, B.V. - Amsterdam

International Classification:

H03H007/40

US Classification:

375231, 375327, 375355, 375362, 370503, 348537

Abstract:

Methods and apparatus for enhanced timing loop are provided for a partial-response maximum-likelihood (PRML) data channel in a direct access storage device (DASD). An acquisition timing circuit for generating an acquisition timing signal includes a plurality of compare functions for receiving and comparing consecutive input signal samples on an interleave with a threshold value. The acquisition timing circuit includes a majority rule voting function coupled to the plurality of compare functions for selecting a timing interleave. Tracking timing circuitry for generating a timing error signal during a read operation includes a channel data detector. The channel data detector receives disk signal input samples and includes a multiple-state path memory. The tracking timing circuit includes a low latency detector receiving disk signal input samples. A selector function is coupled to an output of the low latency detector and is coupled to the multiple-state path memory for selecting a state.

US Patent:

6901119, May 31, 2005

Filed:

Feb 22, 2001

Appl. No.:

09/792325

Inventors:

Roy Daron Cideciyan - Rueschlikon, CH
Jonathan Darrel Coker - Rochester MN, US
Ajay Dholakia - Gattikon, CH
Evangelos S. Eleftheriou - Zurich, CH
Richard Leo Galbraith - Rochester MN, US
Thomas Mittelholzer - Zurich, CH
David James Stanek - Rochester MN, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H04L027/06
H03D001/00

US Classification:

375341, 375291, 714792, 714795, 714796

Abstract:

A method and apparatus are provided for implementing soft-input soft-output iterative detectors/decoders. Soft-input information is added directly to incoming channel samples. Input signals comprising the received incoming channel samples with the added soft-input information are detected using a detector trellis. Branch metric terms are transformed to shift all time varying terms with the added soft-input information and some constant terms after an add compare select (ACS) unit. The shifted time varying terms with the added soft-input information and the shifted constant terms are added directly to state metric terms. The soft-input information is added directly to incoming channel samples and the computation of branch metrics is not affected. This allows optimization of a dual-max detector and soft-input soft-output Viterbi detector architectures to minimize hardware complexity and power consumption.

US Patent:

7193802, Mar 20, 2007

Filed:

Mar 25, 2004

Appl. No.:

10/809230

Inventors:

Roy D. Cideciyan - Rueschlikon, CH
Ajay Dholakia - Gattikon, CH
Evangelos S. Eleftheriou - Zurich, CH
Richard L. Galbraith - Rochester MN, US
Weldon M. Hanson - Rochester MN, US
Thomas Mittelholzer - Zurich, CH
Travis R. Oenning - Rochester MN, US
Michael J. Ross - Rochester MN, US
David J. Stanek - Rochester MN, US

Assignee:

Hitachi Global Storage Technologies Netherlands, B.V. - Amsterdam

International Classification:

G11B 5/09
G11B 5/035
H03K 5/139

US Classification:

360 65, 360 46, 375232

Abstract:

An apparatus for providing dynamic equalizer optimization is disclosed. The present invention solves the above-described problems by providing equalizer coefficient updates that converge towards the same solution as the direct method without having to first write a known pattern to the disk or requiring any prior knowledge of the data already written on the disk. The adaptive cosine function may be used to modify only a DFIR tap set, only the j and k parameters of a cosine equalizer or to modify both the tap set for a DFIR filter and the j and k parameters of the cosine equalizer. Another algorithm, such as the LMS algorithm, may be used to modify parameters not modified by the cosine algorithm.

US Patent:

20020178422, Nov 28, 2002

Filed:

Apr 11, 2001

Appl. No.:

09/833141

Inventors:

Richard Galbraith - Rochester MN, US
Allen Haar - Essex Junction VT, US
David Stanek - Rochester MN, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03M013/03

US Classification:

714/794000, 714/795000

Abstract:

A method and apparatus for maximum likelihood detection of a sequential stream of binary bits. 2binary states (N 2) are projected onto a trellis at a sequence of times. Two branches to each binary state at time Tfrom a closest previous time Tare identified (i N). There are 2such branches between Tand T. A state metric for each of the 2binary states at Tand a branch metric for each of the 2branches between Tand Tare provided. An illegal branch and a legal branch to a state S1 at time Tare so designated. A state metric is computed at each of the 2binary states at time Tas a function of: the state metrics at T, the branch metrics between Tand T, and the 2 branches to state S1.