Dustin T Do

US Patent:

20120032276, Feb 9, 2012

Filed:

Aug 6, 2010

Appl. No.:

12/851805

Inventors:

Dustin Do - Morgan Hill CA, US
Andy Lee - San Jose CA, US
Giles V. Powell - Alameda CA, US
Bradley Jensen - San Jose CA, US
Swee Aun Lau - Penang, MY
Thomas H. White - Santa Clara CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

H01L 29/06
H01L 29/78

US Classification:

257401, 257E29007, 257E29255

Abstract:

Embodiments of N-well or P-well strap structures are disclosed with lower space requirements achieved by forming the strap on both sides of one or more floating polysilicon gate fingers.

US Patent:

20130140640, Jun 6, 2013

Filed:

Aug 4, 2011

Appl. No.:

13/814590

Inventors:

Dustin Do - Morgan Hill CA, US
Andy L. Lee - San Jose CA, US
Giles V. Powell - Alameda CA, US
Bradley Jensen - San Jose CA, US
Swee Aun Lau - Penang, MY

Assignee:

ALTERA CORPORATION - San Jose CA

International Classification:

H01L 27/04

US Classification:

257368

Abstract:

Embodiments of N-well or P-well strap structures are disclosed with lower requirements achieved by forming the strap on both sides of one or more floating polysilicon gate fingers.

US Patent:

20140159157, Jun 12, 2014

Filed:

Dec 7, 2012

Appl. No.:

13/708556

Inventors:

Altera Corporation - , US
Shue Ling Ong - Kuala Sepetang, MY
Dustin Do - Milpitas CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

H01L 27/088
H01L 29/66

US Classification:

257368, 438294, 438299

Abstract:

An integrated circuit with an antenna diode is described. The integrated circuit includes a substrate, a transistor, first and second diffusion regions, and a dummy gate. The transistor and the first and second diffusion regions may be formed within the substrate. The transistor has its gate structure disposed on the substrate. The dummy gate structure may be disposed on a region of the substrate such that it separates the first diffusion region from the second diffusion region. The dummy gate structure may also be coupled to the transistor gate structure.