Eric E Quintana

US Patent:

50758462, Dec 24, 1991

Filed:

Sep 29, 1989

Appl. No.:

7/414335

Inventors:

Russell A. Reininger - Austin TX
William B. Ledbetter - Austin TX
Robin W. Edenfield - Austin TX
Van B. Shahan - Austin TX
Ralph C. McGarity - Austin TX
Eric E. Quintana - Austin TX

Assignee:

Motorola, Inc. - Schaubmurg IL

International Classification:

G06F 906

US Classification:

364200

Abstract:

A data processor having a serialization attribute on a page basis is provided. A set of page descriptors and transparent translation registers encode the serialization attribute as a cache mode. The data processor is a pipelined machine, having at least two function units, which operate independently of each other. The function units issues requests, for access to information stored in an external memory, to an access controller. The access controller serves as an arbitration mechanism, and grants the requests of the function units in accordance with the issuance order of the requests by the function units. When the memory access is marked serialized in the page descriptor, an access controller postpones the serialized access, until the completion of all pending memory accesses in the instruction sequence. All pending requests are then completed in a predetermined order, independent of the issuance order of the requests made by the function units, and all appropriate exception processing is completed. The postponed serialized access is then completed.

US Patent:

53392663, Aug 16, 1994

Filed:

Nov 29, 1993

Appl. No.:

8/158324

Inventors:

Christopher N. Hinds - Austin TX
Eric V. Fiene - Austin TX
Daniel T. Marquette - Austin TX
Eric E. Quintana - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G06F 738

US Classification:

364748

Abstract:

A method and apparatus for detecting and completing floating point operations involving special floating point operands is performed in parallel, via a circuit (24), to the operation of at least one floating point mathematical unit (18, 20or 22). The floating point control (30) along with registers (14 and 16) provide floating point operands and floating point control to the mathematical units (18, 20, and 22). If the mathematical units (18, 20, and 22) cannot perform a proper floating point calculation because of the presence of a special operand, then the circuit (24) will detect the special operand and complete the floating point operation in a proper manner by communicating with the floating point control unit (30).

US Patent:

55396844, Jul 23, 1996

Filed:

Sep 18, 1995

Appl. No.:

8/529469

Inventors:

Eric E. Quintana - Austin TX
Daniel T. Marquette - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G06F 752
G06F 7552

US Classification:

364748

Abstract:

A data processing system (10) has a circuit for determining floating point exponents for divide operations and square root operations. The circuit has two input multiplexers (26 and 28) which provide exponent information or constants to an adder (30). The exponent information and constants are processed by the adder (30) to output three possible exponent values for either a divide operation or a square root operation. The three possible exponent values are stored in three registers (34, 36, and 38). A multiplexer (40) used mantissa rounding and normalizing information to determine which exponent of the three possible exponent values are correct for the current floating point calculation.

US Patent:

20220206791, Jun 30, 2022

Filed:

Dec 24, 2020

Appl. No.:

17/134100

Inventors:

- Santa Clara CA, US
Kameswar Subramaniam - Austin TX, US
Eric Quintana - Austin TX, US

International Classification:

G06F 9/22

Abstract:

Systems, methods, and apparatuses relating to circuitry to implement a cross-lane packed data instruction on a partial (e.g., half) width processor with a minimal number of micro-operations are described. In one embodiment, a hardware processor core includes a decoder circuit to decode a single packed data instruction into only a first micro-operation and a second micro-operation, a packed data execution circuit to execute the first micro-operation and the second micro-operation, and a reservation station circuit coupled between the decoder circuit and the packed data execution circuit, the reservation station circuit comprising a first reservation station entry for the first micro-operation to store a first set of fields that indicate three or more input sources and a first destination, and a second reservation station entry for the second micro-operation to store a second set of fields to indicate three or more input sources and a second destination.