Erick G Walton

US Patent:

6409903, Jun 25, 2002

Filed:

Dec 21, 1999

Appl. No.:

09/469120

Inventors:

Dean S. Chung - Essex Junction VT
Josef W. Korejwa - Charlotte VT
Erick G. Walton - Underhill VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

C25D 500

US Classification:

205 96, 205105, 205157, 205291, 2042295, 204DIG 9, 204922FOR

Abstract:

A method and apparatus are provided for the electroplating of a substrate such as a semiconductor wafer which provides a uniform electroplated surface and minimizes bum-through of a seed layer used on the substrate to initiate electroplating. The method and apparatus of the invention uses a specially defined multistep electroplating process wherein, in one aspect, a voltage below a predetermined threshold voltage is applied to the anode and cathode for a first time period followed by applying a current to the anode and cathode for a second time period the current producing a voltage below the predetermined threshold voltage. In another aspect of the invention, a current is applied to the anode and cathode substrate which current is preprogrammed to ramp up to a current value from a first current value which current produces a voltage below a predetermined threshold voltage. Electroplated articles including copper electroplated semiconductor wafers made using the apparatus and method of the invention are also provided.

US Patent:

6605534, Aug 12, 2003

Filed:

Jun 28, 2000

Appl. No.:

09/605322

Inventors:

Dean S. Chung - Essex Junction VT
David V. Horak - Essex Junction VT
Erick G. Walton - Underhill VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 214763

US Classification:

438674, 438638, 438677, 438678, 438687, 438799

Abstract:

The present invention provides a method of selectively inhibiting the deposition of a conductive material within desired regions of a semiconductor device. A seed layer is rendered ineffective to the electroplating in select regions of the substrate, by either the removal or the poisoning of the seed layer in select regions.

US Patent:

7052925, May 30, 2006

Filed:

Apr 8, 2004

Appl. No.:

10/709039

Inventors:

William J. Murphy - North Ferrisburgh VT, US
Edmund J. Sprogis - Underhill VT, US
Anthony K. Stamper - Williston VT, US
Erick G. Walton - Underhill VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 31/26

US Classification:

438 48, 438210, 438238, 338275, 338330, 296101, 29612

Abstract:

A method for manufacturing a self-compensating resistor within an integrated circuit is disclosed. The self-compensating resistor includes a first resistor and a second resistor. The first resistor having a first resistance value is initially formed, and then the second resistor having a second resistance value is subsequently formed. The second resistor is connected in series with the first resistor. The second resistance value is less than the first resistance value, but the total resistance value of the first and second resistors lies beyond a desired target resistance range. Finally, an electric current is sent to the second resistor to change the dimension of the second resistor such that the total resistance value of the first and second resistors falls within the desired target resistance range.

US Patent:

7207096, Apr 24, 2007

Filed:

Jan 22, 2004

Appl. No.:

10/707896

Inventors:

Jeffrey P. Gambino - Westford VT, US
William T. Motsiff - Essex Junction VT, US
Erick G. Walton - Underhill VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01F 7/127
H01L 21/44

US Classification:

296021, 438612, 438613, 438652, 336200

Abstract:

A method for manufacturing high performance copper inductors includes providing a tall, Cu laminate spiral inductor is formed at the last metal level, and at the last metal +1 level, with the metal levels being interconnected by a bar via having the same spiral shape as the spiral metal inductors at the last metal level and the last metal +1 level. The method includes integrating the formation of thick inductors with the formation of bond pads, terminals and interconnect wiring with the last metal +1 wiring. Included are dielectric deposition and spacer formation steps, and/or selective deposition of a passivating metal such as CoWP, to passivate a Cu inductor that is formed after the last metal layer.

US Patent:

7678258, Mar 16, 2010

Filed:

Jul 10, 2003

Appl. No.:

10/615794

Inventors:

Panayotis Andricacos - Croton-on-Hudson NY, US
Dean S. Chung - Essex Junction VT, US
Hariklia Deligianni - Tenafly NJ, US
James E. Fluegel - Rhinebeck NY, US
Keith T. Kwietniak - Highlandfalls NY, US
Peter S. Locke - Hopewell Junction NY, US
Darryl D. Restaino - Modena NY, US
Philippe M. Vereecken - Sleepy Hollow NY, US
Erick G. Walton - Shelburne VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

C25D 5/00

US Classification:

205 81, 205101

Abstract:

An improved method of stabilizing wet chemical baths is disclosed. Typically such baths are used in processes for treating workpieces, for example, plating processes for plating metal onto substrates. In particular, the present invention relates to copper plating baths. More particularly, the present invention relates to the stability of copper plating baths. More particularly, the present invention relates to prevention of void formation by monitoring the accumulation of deleterious by-products in copper plating baths.

US Patent:

58775897, Mar 2, 1999

Filed:

Mar 18, 1997

Appl. No.:

8/819346

Inventors:

Clifford O. Morgan - Burlington VT
Matthew J. Rutten - Milton VT
Erick G. Walton - South Burlington VT
Terrance M. Wright - Williston VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01J 1749

US Classification:

313582

Abstract:

A gas discharge illumination device is prepared by encapsulating ionizable gas within microporous or nanoscale sealed cavities created within a matrix material. Upon exposure of said matrix material to an electric field, the ionizable gas becomes ionized and emits light. By incorporating several different ionizable gases into one matrix material, a display with different colors of light can be produced. The gas discharge illumination device can be fabricated by a variety of techniques including selective cavity formation with overcoating taking place in an ionizable gas ambient, and bubbling ionizable gas through the matrix material while it is in viscous form. The gas discharge illumination device can be used to form either active or passive displays, as a sensor for detecting electric fields, and in other applications.

US Patent:

60543396, Apr 25, 2000

Filed:

Mar 4, 1997

Appl. No.:

8/810587

Inventors:

Richard A. Gilmour - Colchester VT
Ronald R. Uttecht - Essex Junction VT
Erick G. Walton - South Burlington VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2182

US Classification:

438132

Abstract:

A shortened fuse link is disclosed. The fuse link comprises a first and second interconnect, with interconnects each being substantially longer than deep. The interconnects are disposed toward each other with a insulator region between them. A fusible conductor, spanning the insulator region, is attached at the top of the interconnects. The present device allows the length of the fusible conductor to be shortened, and results in a fuse link that can be consistently blown with a single laser pulse. Additionally, the fuse link can be used in a staggered layout. The staggered layout of parallel fuse links allows a high number of links in a relatively small area, with or without the use of tungsten barriers, and allows accessing all fuse links through a single fuse blow window.

US Patent:

49815300, Jan 1, 1991

Filed:

Nov 28, 1988

Appl. No.:

7/276597

Inventors:

Donna J. Clodgo - Richmond VT
Rosemary A. Previti-Kelly - Richmond VT
Ronald R. Uttecht - Essex Junction VT
Erick G. Walton - South Burlington VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2156
H01L 2147

US Classification:

148 333

Abstract:

An improved insulation layer is formed by first preparing a solution by reacting water with an aminoalkoxysilane monomer in a solvent, using a critical mole ratio of water/monomer. After a sufficient aging period, the solution is coated onto a suitable surface, e. g. the surface of a semiconductor device, and then cured, in an essentially oxygen-free atmosphere, to a ladder-type silsesquioxane polymer. The insulation layer demonstrates excellent planarizing characteristics, while also exhibiting enhanced crack-resistance.