Feng Lijing Zhou

US Patent:

7280567, Oct 9, 2007

Filed:

Mar 10, 2005

Appl. No.:

11/077291

Inventors:

Ningyi Luo - Fremont CA, US
Feng Zhou - Kittanning PA, US
Yuxing Zhao - Suzhou, CN

International Classification:

H01S 3/30

US Classification:

372 6, 372 23

Abstract:

An all-fiber device platform for producing high-power ROGB or RGB laser output comprises an optical fiber including multiple waveguide gain regions embedded within a common inner cladding and within an outer cladding, an optical cavity defined by dielectric reflectors and/or FBG mirrors, and a pump source for exciting one or more active ionic species by one or multiple pump wavelengths from one or both ends of the optical fiber through upconversion process. An apparatus for producing sequential or simultaneous multiple wavelength laser operation provides for applications of color projection displays and biomedical or other instrumentation.

US Patent:

7522651, Apr 21, 2009

Filed:

Feb 7, 2005

Appl. No.:

11/052725

Inventors:

Ningyi Luo - Fremont CA, US
Shaoping Lu - Palo Alto CA, US
Feng Zhou - Kittanning PA, US

Assignee:

Pavilion Integration Corporation - San Jose CA

International Classification:

H01S 3/093
H01S 3/091

US Classification:

372 75, 372 72

Abstract:

Solid-state laser(s) pumped by incoherent, monochromatic light from sources such as LED arrays and integrating technologies such as high power LED arrays and solid-state laser materials in conjunction with efficient and uniform absorption of pumping energies through a diffusing pump chamber. The resulting laser(s) are compact, robust, low-cost, and able to produce high power output for practical applications. It may efficiently operate over wide temperature and performance ranges, at CW or pulse modes, even with ultra short pulse width and/or extremely high repetition rates. Our inventive structure(s) is/are highly flexible and applicable to a large group of lasing media including those with very short upper state life times. Advantageously, they may be applied to a plethora of laser systems at wavelengths that have important applications and unavailable to other direct pumping technologies.

US Patent:

20220231037, Jul 21, 2022

Filed:

Apr 8, 2022

Appl. No.:

17/716950

Inventors:

- San Jose CA, US
CATHERINE DECOBERT - Pourrieres, FR
FENG ZHOU - Fremont CA, US
JINHO KIM - Saratoga CA, US
XIAN LIU - Sunnyvale CA, US
NHAN DO - Saratoga CA, US

International Classification:

H01L 27/11517
H01L 29/423
H01L 29/66
H01L 29/78
H01L 29/788

Abstract:

A method of forming a device on a substrate with recessed first/third areas relative to a second area by forming a fin in the second area, forming first source/drain regions (with first channel region therebetween) by first/second implantations, forming second source/drain regions in the third area (defining second channel region therebetween) by the second implantation, forming third source/drain regions in the fin (defining third channel region therebetween) by third implantation, forming a floating gate over a first portion of the first channel region by first polysilicon deposition, forming a control gate over the floating gate by second polysilicon deposition, forming an erase gate over the first source region and a device gate over the second channel region by third polysilicon deposition, and forming a word line gate over a second portion of the first channel region and a logic gate over the third channel region by metal deposition.

US Patent:

20200176578, Jun 4, 2020

Filed:

Dec 3, 2018

Appl. No.:

16/208288

Inventors:

- San Jose CA, US
Catherine Decobert - Pourrieres, FR
Feng Zhou - Fremont CA, US
Jinho Kim - Saratoga CA, US
Xian Liu - Sunnyvale CA, US
Nhan Do - Saratoga CA, US

International Classification:

H01L 29/423
H01L 29/78
H01L 29/08
H01L 29/10
H01L 27/11521
H01L 29/66
G11C 16/04
G11C 16/10
G11C 16/14
G11C 16/26
H01L 29/788

Abstract:

A memory cell is formed on a semiconductor substrate having an upper surface with a plurality of upwardly extending fins. First and second fins extend in one direction, and a third fin extends in an orthogonal direction. Spaced apart source and drain regions are formed in each of the first and second fins, defining a channel region extending there between in each of the first and second fins. The source regions are disposed at intersections between the third fin and the first and second fins. A floating gate is disposed laterally between the first and second fins, and laterally adjacent to the third fin, and extends along first portions of the channel regions. A word line gate extends along second portions of the channel regions. A control gate is disposed over the floating gate. An erase gate is disposed over the source regions and the floating gate.

US Patent:

20200013786, Jan 9, 2020

Filed:

Jul 5, 2018

Appl. No.:

16/028244

Inventors:

- San Jose CA, US
CATHERINE DECOBERT - Pourrieres, FR
FENG ZHOU - Fremont CA, US
JINHO KIM - Saratoga CA, US
XIAN LIU - Sunnyvale CA, US
NHAN DO - Saratoga CA, US

International Classification:

H01L 27/11524
H01L 29/66
H01L 29/423
H01L 29/78
H01L 29/788
H01L 21/266
H01L 21/768
H01L 21/8234
H01L 21/8238
H01L 27/088

Abstract:

A memory device including a plurality of upwardly extending fins in a semiconductor substrate upper surface. A memory cell is formed on a first of the fins, and includes spaced apart source and drain regions in the first fin, with a channel region extending along top and opposing side surfaces of the first fin between the source and drain regions. A floating gate extends along a first portion of the channel region. A select gate extends along a second portion of the channel region. A control gate extends along the floating gate. An erase gate extends along the source region. A second of the fins has a length that extends in a first direction which is perpendicular to a second direction in which a length of the first fin extends. The source region is formed in the first fin at an intersection of the first and second fins.

US Patent:

20200013788, Jan 9, 2020

Filed:

May 24, 2019

Appl. No.:

16/422740

Inventors:

- San Jose CA, US
Catherine Decobert - Pourrieres, FR
Feng Zhou - Fremont CA, US
Jinho Kim - Saratoga CA, US
Xian Liu - Sunnyvale CA, US
Nhan Do - Saratoga CA, US

International Classification:

H01L 27/11524
H01L 29/66
H01L 21/8238
H01L 21/8234
H01L 21/768
H01L 27/088
H01L 21/266
H01L 29/788
H01L 29/78
H01L 29/423

Abstract:

A method of forming a memory device including a plurality of upwardly extending fins in a semiconductor substrate upper surface. A memory cell is formed on a first fin, and includes spaced apart source and drain regions in the first fin, with a channel region extending along top and opposing side surfaces of the first fin between the source and drain regions. A floating gate extends along a first portion of the channel region. A select gate extends along a second portion of the channel region. A control gate extends along the floating gate. An erase gate extends along the source region. A second fin has a length that extends in a first direction which is perpendicular to a second direction in which a length of the first fin extends. The source region is formed in the first fin at an intersection of the first and second fins.

US Patent:

20180226420, Aug 9, 2018

Filed:

Apr 4, 2018

Appl. No.:

15/945161

Inventors:

- San Jose CA, US
FENG ZHOU - Fremont CA, US
JENG-WEI YANG - Zhubei City, TW
HIEU VAN TRAN - San Jose CA, US
NHAN DO - Saratoga CA, US

International Classification:

H01L 27/11521
H01L 27/11524
H01L 29/788
H01L 29/66
H01L 21/28
H01L 29/423

Abstract:

A memory device including a silicon substrate having a planar upper surface in a memory cell area and an upwardly extending silicon fin in a logic device area. The silicon fin includes side surfaces extending up and terminating at a top surface. The logic device includes spaced apart source and drain regions with a channel region extending there between (along the top surface and the side surfaces), and a conductive logic gate disposed over the top surface and laterally adjacent to the side surfaces. The memory cell includes spaced apart source and drain regions with a second channel region extending there between, a conductive floating gate disposed over one portion of the second channel region, a conductive word line gate disposed over another portion of the second channel region, a conductive control gate disposed over the floating gate, and a conductive erase gate disposed over the source region.

US Patent:

20180033482, Feb 1, 2018

Filed:

May 17, 2017

Appl. No.:

15/597709

Inventors:

- San Jose CA, US
- Connexis, SG
Feng Zhou - Fremont CA, US
Xian Liu - Sunnyvale CA, US
Steven Lemke - Boulder Creek CA, US
Nhan Do - Saratoga CA, US
Zhixian Chen - Fusionopolis Way, SG
Xinpeng Wang - Teban Gardens Road, SG

International Classification:

G11C 13/00
H01L 27/24
H01L 45/00

Abstract:

A memory device includes a metal oxide material disposed between and in electrical contact with first and second conductive electrodes, and an electrical current source configured to apply one or more electrical current pulses through the metal oxide material. For each of the one or more electrical current pulses, an amplitude of the electrical current increases over time during the electrical current pulse to form a conductive filament in metal oxide material.