Frank W Ferraiolo

US Patent:

8018837, Sep 13, 2011

Filed:

Dec 10, 2009

Appl. No.:

12/635121

Inventors:

Wiren D. Becker - New York NY, US
Daniel M. Dreps - Georgetown TX, US
Frank D. Ferraiolo - Essex Junction VT, US
Anand Haridass - Austin TX, US
Robert J. Reese - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01R 31/08

US Classification:

370217, 710305

Abstract:

A method, apparatus, and computer instructions for managing a set of signal paths for a chip. A defective signal path within the set of signal paths for the chip is detected. Signals are re-routed through the set of signal paths such that the defective signal path is removed from the set of signal paths and sending signals using remaining data signal paths in the set of signal paths and using an extra signal path in response to detecting the defective signal path.

US Patent:

20120106687, May 3, 2012

Filed:

Oct 27, 2010

Appl. No.:

12/912883

Inventors:

John F. Bulzacchelli - Yonkers NY, US
Timothy O. Dickson - Danbury CT, US
Frank D. Ferraiolo - Essex Junction VT, US
Robert J. Reese - Austin TX, US
Michael B. Spear - Round Rock TX, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

H04L 7/00

US Classification:

375354

Abstract:

A parallel data link includes a redundant line. A bank of switches permits any arbitrary line of the link to be enabled or disabled for carrying functional data, each line being dynamically calibrated in turn by disabling the line and allowing other lines to carry the functional data. The switches are located downstream of alignment mechanisms so that data input to the switches is compensated for data skew. Preferably, receiver synchronization circuitry in each line operates in a respective independent clock domain, while the switches and calibration mechanism operate in a common clock domain. Preferably, the receiver synchronization circuits provide an adjustable delay corresponding to a variable number of clock cycles to align the outputs of the receiver synchronization circuits with respect to one another, which can accommodate high data skew.