Franklin L Duan

US Patent:

6472715, Oct 29, 2002

Filed:

Sep 28, 2000

Appl. No.:

09/675109

Inventors:

Helmut Puchner - Santa Clara CA
Ruggero Castagnetti - San Jose CA
Weiran Kong - Sunnyvale CA
Lee Phan - Fremont CA
Franklin Duan - Sunnyvale CA
Steven Michael Peterson - Eagan MN

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H01L 2976

US Classification:

257371, 257376, 257387

Abstract:

An integrated circuit structures such as an SRAM construction wherein the soft error rate is reduced comprises an integrated circuit structure formed in a semiconductor substrate, wherein at least one N channel transistor is built in a P well adjacent to one or more deep N wells connected to the high voltage supply and the deep N wells extend from the surface of the substrate down into the substrate to a depth at least equal to that depth at which alpha particle-generated electron-hole pairs can effectively cause a soft error in the SRAM cell. For a 0. 25 m SRAM design having one or more N wells of a conventional depth not exceeding about 0. 5 m, the depth at which alpha particle-generated electron-hole pairs can effectively cause a soft error in the SRAM cell is from 1 to 3 m. The deep N well of the 0. 25 m SRAM design, therefore, extends down from the substrate surface a distance of at least about 1 m, and preferably at least about 2 m.

US Patent:

6977512, Dec 20, 2005

Filed:

Dec 4, 2003

Appl. No.:

10/727719

Inventors:

Franklin Duan - San Jose CA, US
Subramanian Ramesh - Cupertino CA, US
Ruggero Castagnetti - Menlo Park CA, US

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G01R027/08
G01R031/26

US Classification:

324691, 324765, 324766

Abstract:

Test structures are provided for accurately quantifying shared contact resistance. The test structures are built based upon an actual memory cell, which is self-aligning to allow shared contact chains through an array of test cells. A main array of test cells is built to provide a chain of shared contact resistance. Using the main array of test cells, a resistance in the shared contact chain may be measured. Supplemental arrays of test cells is built to provide a chain of poly side resistance, a chain of island side resistance, a chain of island connection line resistance, and a chain of poly connection resistance. A tester measures resistance using the test structures and uses the values to accurately determine shared contact resistance.

US Patent:

6978407, Dec 20, 2005

Filed:

May 27, 2003

Appl. No.:

10/445437

Inventors:

Franklin L. Duan - San Jose CA, US
Subramanian Ramesh - Cupertino CA, US
Ruggero Castagnetti - Menlo Park CA, US

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G11C029/00

US Classification:

714721, 714732

Abstract:

A self-aligning memory cell design is provided to allow testing of transistors in every cell of a memory circuit. A test array of these cells is fabricated with contact pads in each cell for specific components in the cell. Then, metal lines are provided to couple the contact pads in the test array. The whole test array is then probed via these metal lines. Tests may then be performed to detect random and systematic transistor degradation electrically for all cells in the circuit. Different components in the memory design may be tested by providing contact pads for the components of interest and providing metal lines coupling the contact pads.

US Patent:

7190185, Mar 13, 2007

Filed:

Oct 29, 2003

Appl. No.:

10/696320

Inventors:

Franklin Duan - San Jose CA, US
Minxuan Liu - San Jose CA, US
John Walker - Colorado Springs CO, US
Nabil Monsour - Colorado Springs CO, US
Carl Monzel - Eagan MN, US

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G01R 31/02

US Classification:

324763

Abstract:

A test methodology which provides that test structures, such as transistors, are arranged in a plurality of rows. A logic circuit controls which row is to be measured. An incrementer receives a triggering signal and functions as an address adder. Each time the triggering signal rises from 0 to 1, the output of the incrementer increases by 1. The output of the incrementer serves as the address input into a decoder. The decoder is connected to the rows of test structures. Preferably, each test structure contains a control circuit which is controlled by this signal (i. e. , the output of the decoder). If the test structures are transistors, bias to each of the transistors can be applied separately with a common gate, source and well, and measurement can be done with a separate drain node.

US Patent:

7223616, May 29, 2007

Filed:

Jun 4, 2004

Appl. No.:

10/862049

Inventors:

Franklin Duan - San Jose CA, US
Maureen Ardans - Gresham OR, US
Jun Song - Cupertino CA, US

Assignee:

LSI Corporation - Milpitas CA

International Classification:

G01R 31/26
H01L 21/66
H01L 23/58
H01L 29/10

US Classification:

438 18, 257 48, 257E21531, 257E21523

Abstract:

The present invention is test structures in unused areas of semiconductor integrated circuits and methods for designing the same. In an exemplary aspect of the present invention, a method for placing test structures in a semiconductor integrated circuit includes: (a) detecting a dummy area in a semiconductor integrated circuit, the semiconductor integrated circuit including probe pads on a top metal layer; (b) filling the dummy area with active test cells, the active test cells being connected to one another; and (c) connecting each of the active test cells to the probe pads with a metal line.

US Patent:

6442061, Aug 27, 2002

Filed:

Feb 14, 2001

Appl. No.:

09/783653

Inventors:

Weiran Kong - Sunnyvale CA
Gary K. Giust - Cupertino CA
Ramnath Venkatraman - San Jose CA
Franklin Duan - Sunnyvale CA
Ruggero Castagnetti - Menlo Park CA
Steven M. Peterson - Eagan MN
Myron J. Buer - Shakopee MN
Minh Tien Nguyen - San Jose CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G11C 1100

US Classification:

365154, 365188, 365156

Abstract:

A method of forming a memory cell according to the present invention. A first pass gate transistor is formed of a first transistor type. The first pass gate transistor has a gate oxide with a first thickness. The source of the first pass gate transistor is electrically connected to a first bit line, and the drain of the first pass gate transistor is electrically connected to a first state node. The gate of the first pass gate transistor is electrically connected to a memory cell enable line. A second pass gate transistor is also formed of the first transistor type. The second pass gate transistor also has a gate oxide with the first thickness. The source of the second pass gate transistor is electrically connected to a second bit line, and the drain of the second pass gate transistor is electrically connected to a second state node. The gate of the second pass gate transistor is electrically connected to the memory cell enable line. A first state node transistor is also formed of the first transistor type.