Gary Louis Rouse

US Patent:

54598397, Oct 17, 1995

Filed:

Aug 22, 1994

Appl. No.:

8/293930

Inventors:

Jeffery L. Swarts - Falls Church VA
Gary L. Rouse - Manassas VA

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 932
G06F 1312

US Classification:

395650

Abstract:

A queue pointer manager contained in an integrated data controller is capable of controlling high speed data transfers between a high speed controlled data channel, a local processor bus and a dedicated local data bus. The overall design utilizes enhanced features of the Micro Channel architecture and data buffering to achieve maximum burst rates of 80 megabytes and to allow communications with 8, 16, 32 and 64 bit Micro Channel devices. Queued demands allow flexible programming of the Micro Channel master operations and reporting of completion statuses. The hardware control of command and status queuing functions increases the processing speed of control operations and reduces the need for software queuing. Extensive error checking/reporting, programming parameters, internal wrap self-test capability give the integrated data controller advanced functions as an input/output processor. The queue pointer manager also manages queue read and write pointers.

US Patent:

55618065, Oct 1, 1996

Filed:

Mar 7, 1994

Appl. No.:

8/206290

Inventors:

John A. Fitchett - Centreville VA
Thomas J. Hahn - Vienna VA
Gary L. Rouse - Manassas VA

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 300

US Classification:

395800

Abstract:

An apparatus for facilitating the transfer of data between computers of different types and architectures is disclosed. The Serial Channel Adapter (SCA) includes four primary functional components: 1) low-end parallel bus interface; 2) data staging buffer; 3) serial interface; and 4) adapter controller, all of which are under microprocessor control and fully programmable to achieve maximum flexibility. Two buses are provided, a Local Data Bus and Local Processor Bus, to minimize processor overhead on the data bus and maximize data throughput.