Gene L Haviland from San Diego, CA

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Non-Volatile Analog Memory Circuit With Closed-Loop Control
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US Patent:

H1359, Mar 3, 1992
Filed:

Jun 20, 1990
Appl. No.:

7/541235
Inventors:

Gene L. Haviland - San Diego CA
Patrick A. Shoemaker - Lemon Grove CA
James R. Feeley - San Diego CA
Alfons Tuszynski - San Diego CA
Assignee:

The United States of America as represented by the Secretary of the Navy - Washington DC
International Classification:

G11C 2700
US Classification:

365 45
Abstract:

A non-volatile analog memory circuit includes charge depositing and storing ircuitry, voltage sensing circuitry, and closed-loop control circuitry. The charge depositing and storing circuitry includes a floating gate operable to receive charge deposited on it. The voltage sensing circuitry supplies an analog output in response to the sensed gate potential. The closed-loop control circuitry is used to control charge deposition. The control circuitry is operable to change the charge on the gate by directing electrical pulses of appropriate polarity to the charge depositing and storing circuitry. This is done to diminish the error between the analog output signal of the charge sensing circuitry and an analog input signal for providing a substantially accurate representation of the analog input signal.

Cmos Analog Four-Quadrant Multiplier
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US Patent:

49068733, Mar 6, 1990
Filed:

Jan 12, 1989
Appl. No.:

7/297452
Inventors:

Patrick A. Shoemaker - Lemon Grove CA
Gene L. Haviland - San Diego CA
Isaac Lagnado - San Diego CA
Assignee:

The United States of America as represented by the Secretary of the Navy - Washington DC
International Classification:

H03L 500
H03K 1901
US Classification:

307498
Abstract:

A four-quadrant analog multiplier circuit provides an output which is proportional to two voltage inputs. The circuit includes a pair of depletion mode transistors having gain constants equal in magnitude and threshold voltages equal in magnitude. The gates of the transistors are coupled in common. One input is applied to the common gates. The other input and its inverse are separately applied to source/drain terminals of the two transistors.

Gene L Haviland