Hai Fung Ho

US Patent:

7971440, Jul 5, 2011

Filed:

May 2, 2008

Appl. No.:

12/114011

Inventors:

Gary K. Chan - Palo Alto CA, US
Hai Ho - San Jose CA, US
Joseph Jacques - Austin TX, US

Assignee:

Cisco Technology, Inc. - San Jose CA

International Classification:

F25B 21/02

US Classification:

62 37, 62 33, 62 36

Abstract:

A voltage regulator is configured to receive an input voltage from a power supply, measure a temperature associated with a heat transfer medium, produce an output voltage to drive a thermo-electric cooler, and vary the output voltage in accordance with changes in the measured temperature. Varying the output voltage results in: 1) extracting of heat from the heat transfer medium when the measured temperature is above a threshold value, or 2) supplying of heat to the heat transfer medium when the measured temperature is below a threshold value. The voltage regulator can cap upper and lower bounds of the output voltage to prevent the thermo-electric cooler from reaching its saturation point. The voltage regulator can be configured to produce an output voltage having reduced voltage ripple.

US Patent:

55008186, Mar 19, 1996

Filed:

Oct 29, 1993

Appl. No.:

8/145373

Inventors:

Shuen C. Chang - San Jose CA
Hai D. Ho - Milpitas CA
Szu C. Sun - Mountain View CA

Assignee:

Sun Microsystems, Inc. - Mountain View CA
Samsung Semiconductor, Inc. - San Jose CA

International Classification:

G11C 700

US Classification:

36518905

Abstract:

A frame buffer including an array of memory cells, circuitry for accessing the memory cells to derive selected pixel data, and output circuitry for providing data signals at an output port, the output circuitry including circuitry for determining the precise time required for a data signal to rise and fall at the output port, such circuitry being selected to provide the minimum delay between succeeding data signals at the output port.

US Patent:

54427487, Aug 15, 1995

Filed:

Oct 29, 1993

Appl. No.:

8/145754

Inventors:

Shuen C. Chang - San Jose CA
Hai D. Ho - Milpitas CA
Szu C. Sun - Mountain View CA

Assignee:

Sun Microsystems, Inc. - Mountain View CA
Samsung Semiconductor Inc. - San Jose CA

International Classification:

G06F 1200

US Classification:

395164

Abstract:

A frame buffer including a plurality of array planes of memory cells, row decoding circuitry for selecting rows of memory cells in each of the array planes to be accessed, column decoding circuitry for selecting columns of memory cells in each of the array planes to be accessed, a plurality of bitlines associated with the columns of memory cells of each array plane, each of the bitlines connecting to a column of memory cells and including a bitline sensing amplifier and a column select switch for providing access to the memory cells of that column of the array plane, a plurality of output sense amplifiers adapted to be connected to a selected number of bitlines in an array plane by closing of particular ones of the column select switches in the bitlines, first apparatus for providing output signals from the plurality of output sense amplifiers associated with each array plane to a data bus, and second apparatus for providing output signals from the plurality of output sense amplifiers associated with each array plane to a shift register.

US Patent:

55287514, Jun 18, 1996

Filed:

Sep 7, 1995

Appl. No.:

8/524474

Inventors:

Curtis Priem - Fremont CA
Shuen C. Chang - San Jose CA
Hai D. Ho - Milpitas CA
Szu C. Sun - Mountain View CA

Assignee:

Sun Microsystems, Inc. - Mountain View CA
Samsung Semiconductor, Inc. - San Jose CA

International Classification:

G06F 1200

US Classification:

395164

Abstract:

A frame buffer designed to be coupled to a data bus and to an output display in a computer system, the frame buffer including an array of memory cells for storing data indicating pixels to be displayed on the output display, address decoding apparatus for controlling access to the array, the address decoding apparatus including column address decoding apparatus for selecting groups of adjacent columns of the array, a plurality of apparatus for selectively writing to each of the columns of any of said groups of adjacent columns, a plurality of color value registers, latching apparatus for storing pixel data equivalent to a row of pixel data to be displayed on the output display, apparatus for writing pixel data from selected groups of adjacent columns of the array to the latching apparatus, and apparatus for connecting either selected ones of the color value registers, the latches, or the data bus to the apparatus for selectively writing to each of the columns of any of said groups of adjacent columns.

US Patent:

55394302, Jul 23, 1996

Filed:

Oct 29, 1993

Appl. No.:

8/145483

Inventors:

Curtis Priem - Fremont CA
Shuen C. Chang - San Jose CA
Hai D. Ho - Milpitas CA

Assignee:

Sun Microsystems, Inc. - Mountain View CA
Samsung Semiconductor, Inc. - San Jose CA

International Classification:

G09G 102

US Classification:

345185

Abstract:

A frame buffer including an array of memory cells for storing data indicating pixels to be displayed on the output display, row addressing decoding apparatus and column address decoding apparatus for selecting memory cells positioned in the array, apparatus for transferring a row address to the row addressing decoding apparatus upon the assertion of a row address strobe signal, apparatus for transferring a column address to the column address decoding apparatus for decoding upon the assertion of a first column address strobe signal, apparatus for latching a column address and any data necessary to complete the access during the first column address strobe signal, apparatus for accessing the particular column the address of which has been latched during the latching of a next subsequent address of a column to be accessed along with any data necessary to complete the next access during the next subsequent column address strobe signal following the first column address strobe signal.

US Patent:

55331874, Jul 2, 1996

Filed:

Oct 29, 1993

Appl. No.:

8/145755

Inventors:

Curtis Priem - Fremont CA
Shuen C. Chang - San Jose CA
Hai D. Ho - Milpitas CA

Assignee:

Sun Microsystems, Inc - Mountain View CA
Samsung Semiconductor, Inc. - San Jose CA

International Classification:

G06F 1200

US Classification:

395164

Abstract:

A frame buffer having a memory array, circuitry for accessing the array, a plurality of color value registers for storing a plurality of color values which may be written to the array, and circuitry for writing to the memory cells a data representing a single pixel, for writing simultaneously to the memory cells data representing a number of pixels equal to the number of conductors on the data bus, or for writing simultaneously to the memory cells data representing an entire row of pixels of the array.

US Patent:

56547420, Aug 5, 1997

Filed:

May 26, 1995

Appl. No.:

8/451476

Inventors:

Curtis Priem - Fremont CA
Chris Malachowsky - Santa Clara CA
Shuen Chin Chang - San Jose CA
Hai Duy Ho - Milpitas CA

Assignee:

Sun Microsystems, Inc. - Mountain View CA
Samsung Semiconductor, Inc. - San Jose CA

International Classification:

G09G 500

US Classification:

345185

Abstract:

A frame buffer designed to allow frame buffer operations which do not involve new row addresses to be accomplished without the need for a RAS cycle. The elimination of RAS cycles for address loading and similar functions substantially accelerates the operation of the frame buffer both as to functions which do not involve memory array addresses and those which do involve memory array addresses.