Hong Li X Jiang

US Patent:

6538832, Mar 25, 2003

Filed:

Jun 7, 2000

Appl. No.:

09/589429

Inventors:

Indumini W. Ranmuthu - Plano TX
Hong Jiang - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G11B 509

US Classification:

360 46, 360 67, 360 63

Abstract:

In hard disk drives (HDD), a magnetic read head moves over a portion of the hard disk when reading data. A preamplifier, having an initial amplification stage of the single ended type, connects to the magnetic read head and amplifies a data signal picked up by the magnetic read head. The preamplifier typically has multiple read heads, or channels. In order to reduce noise coming into the read channels of the preamplifier from the substrate capacitances of the input transistors connected to the read heads, the input transistors are grouped together into multiple banks that are multiplexed, or turn on separately. To further aid noise reduction, the poles of the single ended amplifier are matched, that is, the frequency response of the constant voltage side is matched to the frequency response to the signal side. This effectively reduces both ground noise and Vcc power supply noise as the the noise becomes common mode on the inputs to a differential amplifier that is connected to the single ended amplifier. Noise is further minimized by connecting the substrates of the switching transistors connected to the input transistors to magnetic read ground, as opposed to integrated circuit ground.

US Patent:

6621649, Sep 16, 2003

Filed:

Nov 10, 2000

Appl. No.:

09/709699

Inventors:

Hong Jiang - Plano TX
Indumini Ranmuthu - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G11B 502

US Classification:

360 67, 360 46

Abstract:

The present invention relates to a preamplifier circuit comprising a plurality of amplifier stages coupled together and operable to consecutively amplify a signal associated with a head of a hard disk drive. The preamplifier circuit further comprises a power delivery circuit operably coupled to the amplifier stages and operable to provide power to the amplifier stages in a substantially concurrent manner when the hard disk drive is transitioning from a write state to a read state. In addition, the circuit comprises a control circuit operably coupled to the amplifier stages, and operable to activate at least two of the plurality of amplifier stages in a generally consecutive manner after the providing of power to the amplifier stages. In the above manner a saturation of an output of the preamplifier circuit is avoided by preventing substantially a propagation of glitches through the preamplifier circuit and providing for a substantially fast write-to-read transition time.

US Patent:

6687064, Feb 3, 2004

Filed:

Jul 21, 2000

Appl. No.:

09/621107

Inventors:

Hong Jiang - Plano TX
Paul Merle Emerson - Murphy TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G11B 509

US Classification:

360 31, 360 68, 360 46, 369 5342, 340652

Abstract:

A circuit ( ) and method for detecting faults of a write head ( ) of a hard-disk drive system ( ). A first resistor R and a second resistor R are coupled to coil L of write head ( ). A transistor Q is coupled to a common node of resistor R and R. Current I is applied to the coil L, and voltages V and V across the nodes at either end of resistors R and R are analyzed in order to detect faults on write head coil L. The detection is performed during a quiet mode of the hard-disk drive system ( ), so the fault detection is frequency-independent. Open faults are distinguishable from short-to-ground faults by the write fault detection circuit ( ).

US Patent:

6707629, Mar 16, 2004

Filed:

Jun 30, 2000

Appl. No.:

09/608896

Inventors:

Hong Jiang - Plano TX
Paul Merle Emerson - Murphy TX
Bryan E. Bloodworth - Irving TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G11B 509

US Classification:

360 67, 360 68

Abstract:

A digital temperature monitor (DTM ( ) includes a proportional-to-absolute temperature (PTAT) sensor ( ) and reference circuit ( ) coupled to the inputs of a comparator ( ). The DTM ( ) monitors the temperature of adjacent and/or proximate integrated circuitry. The method includes the steps of providing a reference signal to the comparator ( ), increasing the reference signal voltage, and determining the temperature of an integrated circuit by determining when the reference signal is greater than the PTAT sensor ( ) output voltage. The DTM ( ) may be implemented as part of a hard-disk drive preamplifier circuit ( ).

US Patent:

6724556, Apr 20, 2004

Filed:

Jun 29, 2001

Appl. No.:

09/896387

Inventors:

Indumini W. Ranmuthu - Plano TX
Hong Jiang - Santa Clara CA

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G11B 503

US Classification:

360 66, 360 67, 360 46

Abstract:

A differential circuit to read differential data from a disk by a voltage bias includes a read circuit having a read circuit pole to read the differential data from the disk by maintaining the voltage bias and a feedback circuit having a feedback pole to sense deviations in the voltage and to adjust the voltage in response to the deviations. The read circuit pole is separated from the feedback pole in frequency.

US Patent:

7134097, Nov 7, 2006

Filed:

Mar 6, 2003

Appl. No.:

10/383120

Inventors:

Zhubiao Zhu - Fort Collins CO, US
Hong Jiang - Plano TX, US
John R. Spencer - Fort Collins CO, US
Michael A Buckley - Fort Collins CO, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 17/50

US Classification:

716 1, 716 4, 716 11

Abstract:

A configurable metal register of an integrated circuit that allows a register output value to be changed by changing any metal or any contact within a metal pattern solution of the register. More than one metal and/or corresponding contact within the metal pattern solution may be changed so that the register output value is correspondingly changed.

US Patent:

61920886, Feb 20, 2001

Filed:

Mar 31, 1998

Appl. No.:

9/052455

Inventors:

Ahmad K. Aman - Fairfax VA
Cecil William Farrow - Highlands Borough NJ
Hong Jiang - Montclair NJ
Agesino Primatic - Frenchtown NJ
Charles Albert Webb - Rumson Borough NJ

Assignee:

Lucent Technologies Inc. - Murray Hill NJ

International Classification:

H04L 2714
H04L 2716
H04L 2722

US Classification:

375326

Abstract:

A digital carrier recovery system includes at least two modes of operation, namely, an acquisition mode and a tracking mode. The bandwidth of the carrier recovery loop filter is different for the acquisition mode and the tracking mode. In the acquisition mode, the digital phase-locked loop seeks and locks to the long term frequency offset of the received carrier signal. In the tracking mode, the digital phase-locked loop tracks the instantaneous variations in the carrier phase. Switching between the acquisition mode and the tracking mode is realized digitally, and includes programmable hysteresis, resulting in optimal performance in the presence of signals having high levels of phase noise (jitter). More specifically, the carrier recovery loop filter "locks" to the pilot signal of an incoming signal, e. g. , a vestigial side band (VSB) video signal, by employing a so-called digital vector tracking phase-locked loop that demodulates the VSB signal.

US Patent:

61342769, Oct 17, 2000

Filed:

Mar 31, 1998

Appl. No.:

9/052454

Inventors:

Ahmad K. Aman - Fairfax VA
Cecil William Farrow - Highlands Borough NJ
Hong Jiang - Montclair NJ
Agesino Primatic - Frenchtown NJ
Charles Albert Webb - Rumson Borough NJ

Assignee:

Lucent Technologies Inc. - Murray Hill NJ

International Classification:

H04L 2714

US Classification:

375326

Abstract:

A digital timing recovery system advantageously employs both demodulated I-phase and Q-phase components to more accurately locate the synchronization signal of an incoming VSB signal. The Q-phase component is advantageously employed to detect the phase error. The use of the Q-phase component provides a more accurate measure of the phase error and results in a larger (wider) acquisition range for timing frequency offset. More specifically, the timing recovery system of this invention performs symbol clock recovery based on the VSB signal segment synchronization (sync) signal and generates a pulse density modulated (PDM) phase difference signal that controls a voltage controlled crystal oscillator (VCXO) in the phase-locked loop. This is realized, in one embodiment of the invention, by correlating received sync segment data with the known sync signal pattern and searching for "peaks" in the correlation values that are periodic at the known sync segment data rate. Once the sync pattern is found, the correlation values for adjacent samples are advantageously employed to generate the necessary feedback control signal value for the VCXO.