Hong Li Jiang

US Patent:

6538832, Mar 25, 2003

Filed:

Jun 7, 2000

Appl. No.:

09/589429

Inventors:

Indumini W. Ranmuthu - Plano TX
Hong Jiang - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G11B 509

US Classification:

360 46, 360 67, 360 63

Abstract:

In hard disk drives (HDD), a magnetic read head moves over a portion of the hard disk when reading data. A preamplifier, having an initial amplification stage of the single ended type, connects to the magnetic read head and amplifies a data signal picked up by the magnetic read head. The preamplifier typically has multiple read heads, or channels. In order to reduce noise coming into the read channels of the preamplifier from the substrate capacitances of the input transistors connected to the read heads, the input transistors are grouped together into multiple banks that are multiplexed, or turn on separately. To further aid noise reduction, the poles of the single ended amplifier are matched, that is, the frequency response of the constant voltage side is matched to the frequency response to the signal side. This effectively reduces both ground noise and Vcc power supply noise as the the noise becomes common mode on the inputs to a differential amplifier that is connected to the single ended amplifier. Noise is further minimized by connecting the substrates of the switching transistors connected to the input transistors to magnetic read ground, as opposed to integrated circuit ground.

US Patent:

6621649, Sep 16, 2003

Filed:

Nov 10, 2000

Appl. No.:

09/709699

Inventors:

Hong Jiang - Plano TX
Indumini Ranmuthu - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G11B 502

US Classification:

360 67, 360 46

Abstract:

The present invention relates to a preamplifier circuit comprising a plurality of amplifier stages coupled together and operable to consecutively amplify a signal associated with a head of a hard disk drive. The preamplifier circuit further comprises a power delivery circuit operably coupled to the amplifier stages and operable to provide power to the amplifier stages in a substantially concurrent manner when the hard disk drive is transitioning from a write state to a read state. In addition, the circuit comprises a control circuit operably coupled to the amplifier stages, and operable to activate at least two of the plurality of amplifier stages in a generally consecutive manner after the providing of power to the amplifier stages. In the above manner a saturation of an output of the preamplifier circuit is avoided by preventing substantially a propagation of glitches through the preamplifier circuit and providing for a substantially fast write-to-read transition time.

US Patent:

6687064, Feb 3, 2004

Filed:

Jul 21, 2000

Appl. No.:

09/621107

Inventors:

Hong Jiang - Plano TX
Paul Merle Emerson - Murphy TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G11B 509

US Classification:

360 31, 360 68, 360 46, 369 5342, 340652

Abstract:

A circuit ( ) and method for detecting faults of a write head ( ) of a hard-disk drive system ( ). A first resistor R and a second resistor R are coupled to coil L of write head ( ). A transistor Q is coupled to a common node of resistor R and R. Current I is applied to the coil L, and voltages V and V across the nodes at either end of resistors R and R are analyzed in order to detect faults on write head coil L. The detection is performed during a quiet mode of the hard-disk drive system ( ), so the fault detection is frequency-independent. Open faults are distinguishable from short-to-ground faults by the write fault detection circuit ( ).

US Patent:

6707629, Mar 16, 2004

Filed:

Jun 30, 2000

Appl. No.:

09/608896

Inventors:

Hong Jiang - Plano TX
Paul Merle Emerson - Murphy TX
Bryan E. Bloodworth - Irving TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G11B 509

US Classification:

360 67, 360 68

Abstract:

A digital temperature monitor (DTM ( ) includes a proportional-to-absolute temperature (PTAT) sensor ( ) and reference circuit ( ) coupled to the inputs of a comparator ( ). The DTM ( ) monitors the temperature of adjacent and/or proximate integrated circuitry. The method includes the steps of providing a reference signal to the comparator ( ), increasing the reference signal voltage, and determining the temperature of an integrated circuit by determining when the reference signal is greater than the PTAT sensor ( ) output voltage. The DTM ( ) may be implemented as part of a hard-disk drive preamplifier circuit ( ).

US Patent:

6724556, Apr 20, 2004

Filed:

Jun 29, 2001

Appl. No.:

09/896387

Inventors:

Indumini W. Ranmuthu - Plano TX
Hong Jiang - Santa Clara CA

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G11B 503

US Classification:

360 66, 360 67, 360 46

Abstract:

A differential circuit to read differential data from a disk by a voltage bias includes a read circuit having a read circuit pole to read the differential data from the disk by maintaining the voltage bias and a feedback circuit having a feedback pole to sense deviations in the voltage and to adjust the voltage in response to the deviations. The read circuit pole is separated from the feedback pole in frequency.

US Patent:

20200028597, Jan 23, 2020

Filed:

Dec 31, 2018

Appl. No.:

16/237578

Inventors:

- Plano TX, US
Hong Jiang - Kernersville NC, US

Assignee:

Futurewei Technologies, Inc. - Plano TX

International Classification:

H04B 17/10
H04B 1/40

Abstract:

A system and method for transmitting and for detecting a transmission power level of a carrier of aggregated carrier signals is configured to generate a plurality of carrier signals as a carrier aggregated signal and to generate an outgoing radio frequency (RF) signal based on the carrier aggregated signal and to produce a feedback signal based the outgoing RF signal. The system process the feedback signal by down converting a first carrier signal within the feedback signal from RF, canceling a down converted harmonically-related signal or an ADC Fs related signal of a second carrier of the carrier aggregated signal and producing a signal representative of the output power of the first carrier of the carrier aggregated signal within the feedback signal.

US Patent:

20170230067, Aug 10, 2017

Filed:

Feb 5, 2016

Appl. No.:

15/016909

Inventors:

- Plano TX, US
Hong Jiang - Kernersville NC, US

International Classification:

H04B 1/04
H04W 24/08

Abstract:

A transmitter includes a power amplifier coupled to amplify an input signal and provide an output signal. A radio frequency coupler is coupled to receive the output signal and provide a measured signal on a coupler output. A measurement receiver multiplexor is coupled to receive the measured signal on the coupler output to produce either a non-phase adjusted signal or a phase adjusted signal on one of a plurality of multiplexor outputs. Multiple receiver paths are coupled to the plurality of multiplexor outputs to receive either the non-phase adjusted signal or the phase adjusted signal. Receive path processing circuitry is configured to produce in-phase and quadrature phase digital signals based on the plurality of multiplexor outputs to digital processing circuitry to cancel 3or 3and 5order measurement receiver distortions.

US Patent:

20170111191, Apr 20, 2017

Filed:

Oct 15, 2015

Appl. No.:

14/884578

Inventors:

- Plano TX, US
Hong Jiang - Kernersville NC, US

International Classification:

H04L 25/06

Abstract:

A method for clock spur artifact correction includes obtaining a plurality of switching stage input signals generated in accordance with an input signal level of an external amplifier, and adjusting the plurality of switching stage input signals such that a clock spur harmonic artifact is reduced. The clock spur harmonic artifact includes a first clock spur harmonic artifact generated in a plurality of external signal paths including external switching stages, and the adjusting the plurality of switching stage input signals includes one of: adjusting a duty ratio of one of the plurality of switching stage input signals in accordance with a gain mismatch between two of the external signal paths; and injecting a first Continuous Wave (CW) signal into the plurality of switching stage input signals in accordance with a previous amplitude of the first clock spur harmonic artifact.