Hui Y Peng

US Patent:

7148075, Dec 12, 2006

Filed:

Jun 5, 2004

Appl. No.:

10/862086

Inventors:

Hui Peng - Fremont CA, US
Wei Luo - Beijing, CN

International Classification:

H01L 21/00

US Classification:

438 22, 438 47

Abstract:

The vertical semiconductor chips or devices have all of advantages of flip chip technique and without its disadvantages. The present invention discloses methods of mass production of the vertical semiconductor chips or devices comprising GaN, GaInP, and GaInNP based LEDs with higher crystal quality, higher throughput, higher yield, and lower cost. The methods comprise the following process steps in the order presented: growing a first-type cladding layer, disposing a reflector/Ohmic layer, disposing a second intermediate layer, disposing an electrically conductive supporting plate, removing the original substrate and the first-type cladding layer exposed, growing an epitaxial layer comprising an active layer and a second-type cladding layer, disposing a second-electrode, and dicing into individual dies.

US Patent:

20050110040, May 26, 2005

Filed:

Nov 26, 2003

Appl. No.:

10/723046

Inventors:

Hui Peng - Fremont CA, US

International Classification:

H01L031/0328

US Classification:

257190000

Abstract:

Lattice mismatch is a critical issue for semiconductor devices including nitride LED. Texturing a substrate, texturing an epitaxial layer, and a method are disclosed in the present invention for localizing and minimizing the effects of lattice mismatch. Texturing may be applied for more than once on the same epitaxial wafer. Thus different epitaxial layers comprising different active layers may be grown on the same wafer and, therefore, the semiconductor device may emit light of a combination of different wavelengths.

US Patent:

20050133806, Jun 23, 2005

Filed:

Dec 17, 2003

Appl. No.:

10/738791

Inventors:

Hui Peng - Fremont CA, US
Gang Peng - Fremont CA, US

International Classification:

H01L029/22

US Classification:

257099000

Abstract:

Based on the unique properties of the flip chip packaging process and GaN based LEDs with transparent substrates, new principles and methods for designing the layout of P contact pads and N contact pads are disclosed. The new designs of the present invention drastically increase the light extraction efficiency of LEDs by reducing the current crowding effect, increasing the uniformity of the spreading current in the active layer, and utilizing most of the available light emitting semiconductor material of the active layer. The present invention combined with the flip chip packaging process significantly improves the LEDs' heat dissipation.

US Patent:

20050161779, Jul 28, 2005

Filed:

Jan 26, 2004

Appl. No.:

10/765346

Inventors:

Hui Peng - Fremont CA, US
Gang Peng - Fremont CA, US

International Classification:

H01L021/44
H01L023/02
H01L029/40

US Classification:

257678000, 438106000, 438108000, 257778000

Abstract:

The present invention discloses new flip chip assemblies and lamps for high power semiconductor chips or devices including GaN LEDs and a new wafer level flip chip packaging process for cost effectively manufacturing the same. The advantages of the new flip chip assemblies, lamps, and the wafer level flip chip package process are: (1) the fabricating process is simpler; (2) no need for expensive flip chip equipments; (3) the throughput is higher; (4) eliminating lattice mismatch between the substrate and the epitaxial layer by removing the substrate; (5) better thermal dissipation; (6) reduced current crowding effect and higher current density; (7) higher light extraction efficiency; (8) eliminating the totally internal reflection; and (9) eliminating the Fresnel reflection at the dome-air interface.

US Patent:

20050189551, Sep 1, 2005

Filed:

Feb 26, 2004

Appl. No.:

10/787816

Inventors:

Hui Peng - Fremont CA, US
Gang Peng - Fremont CA, US

International Classification:

H01L033/00

US Classification:

257094000

Abstract:

High power and high brightness light emitting diode (LED) assemblies emitting white light are disclosed. The present invention also discloses methods for cost effective mass production of the high power and high brightness LED assemblies with high throughput.

US Patent:

20060124956, Jun 15, 2006

Filed:

Dec 13, 2004

Appl. No.:

11/010514

Inventors:

Hui Peng - Fremont CA, US

International Classification:

H01L 33/00
H01L 21/00

US Classification:

257103000, 257014000, 438022000, 257094000

Abstract:

The present invention discloses the large area high quality quasi group III-nitride substrates comprising two categories: electrically conductive and isolating. The methods manufacturing the same comprise the following process steps in the order presented: disposing a first intermediate layer on a large area silicon (Si) original growth substrate, disposing a group III-nitride epitaxial layer including a n- or p-type epitaxial layer, disposing a reflector/Ohmic layer, disposing a second intermediate layer, disposing a supporting plate, removing the silicon original growth substrate and the first intermediate layer, then the group III-nitride epitaxial layer exposed. Vertical and lateral GaN based LEDs growing on electrically conductive and isolating quasi group III-nitride substrates respectively are disclosed.

US Patent:

20070272939, Nov 29, 2007

Filed:

May 25, 2007

Appl. No.:

11/807121

Inventors:

Hui Peng - Fremont CA, US

International Classification:

H01L 33/00

US Classification:

257 99

Abstract:

The present invention discloses tunnel vertical semiconductor devices and chips comprising tunnel vertical GaN based, GaP based and ZnO based LEDs and manufacturing method. The structure of an embodiment of tunnel vertical semiconductor devices and chips is the following: first and second electrodes formed on first surface of a supporting silicon chip; third and fourth electrodes formed on second surface of the supporting silicon chip. First and second electrodes are respectively electrically connected with third and fourth electrodes. The position and shape of second electrode correspond to that of the reflector/Ohmic/bonding layer of a semiconductor chip, while the position and shape of first electrode is corresponded to that of a protection plug. A half-tunnel-metal-plug electrically connects a patterned electrode deposited on a current spreading layer to the first electrode on the first surface of the supporting silicon chip.

US Patent:

20080033288, Feb 7, 2008

Filed:

Jun 25, 2007

Appl. No.:

11/821601

Inventors:

Shih-Ping Wang - Los Altos CA, US
Jiayu Chen - Palo Alto CA, US
Hui Peng - Santa Clara CA, US

International Classification:

A61B 8/08

US Classification:

600427000, 382128000, 600437000

Abstract:

Method and related apparatuses are described for performing automated ultrasound mammography with reduced nipple shadow effects. The breast is compressed in a direction generally toward the chest wall of the patient with one side of a compressive member which is preferably a membrane. The breast is scanned with an ultrasonic transducer array positioned in acoustic communication with the other side of the membrane. Beamsteering is used. The signals from the beamsteered energy are combined to generate one or more compound images having a reduced nipple shadow effect. An acoustic couplant is preferably applied between the breast and the membrane. The images of the sub-nipple region are also preferably enhanced by making comparisons with reference areas of the breast in areas away from the nipple shadow effected area. The images are preferably displayed to a user, either automatically or upon receiving a preference from the user.