Huy T Vo

US Patent:

6434066, Aug 13, 2002

Filed:

Aug 28, 2001

Appl. No.:

09/941021

Inventors:

William K. Waller - Garland TX
Huy T. Vo - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 700

US Classification:

365200, 365207, 3652257, 36523003

Abstract:

A redundancy architecture for repairing a DRAM includes fuse banks for storing the row addresses of defective rows in sub-arrays of the DRAM. Row decoders activate a redundant row in one of the sub-arrays in response to receiving a row address matching one of the stored defective row addresses and, at the same time, disable a redundant row in the other of the sub-arrays that is arranged in an order complementary to that of the activated redundant row.

US Patent:

6574156, Jun 3, 2003

Filed:

Aug 5, 2002

Appl. No.:

10/213121

Inventors:

William K. Waller - Garland TX
Huy T. Vo - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 700

US Classification:

365200, 365207, 3652257, 36523003

Abstract:

A redundancy architecture for repairing a DRAM includes fuse banks for storing the row addresses of defective rows in sub-arrays of the DRAM. Row decoders activate a redundant row in one of the sub-arrays in response to receiving a row address matching one of the stored defective row addresses and, at the same time, disable a redundant row in the other of the sub-arrays that is arranged in an order complementary to that of the activated redundant row.

US Patent:

6693833, Feb 17, 2004

Filed:

May 22, 2003

Appl. No.:

10/443472

Inventors:

William K. Waller - Garland TX
Huy T. Vo - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 700

US Classification:

365200, 365201, 3652257, 36523003

Abstract:

A redundancy architecture for repairing a DRAM includes fuse banks for storing the row addresses of defective rows in sub-arrays of the DRAM. Row decoders activate a redundant row in one of the sub-arrays in response to receiving a row address matching one of the stored defective row addresses and, at the same time, disable a redundant row in the other of the sub-arrays that is arranged in an order complementary to that of the activated redundant row.

US Patent:

60058137, Dec 21, 1999

Filed:

Nov 12, 1997

Appl. No.:

8/968439

Inventors:

William K. Waller - Garland TX
Huy T. Vo - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 700

US Classification:

365200

Abstract:

A redundancy architecture for repairing a DRAM includes fuse banks for storing the row addresses of defective rows in sub-arrays of the DRAM. Row decoders activate a redundant row in one of the sub-arrays in response to receiving a row address matching one of the stored defective row addresses and, at the same time, disable a redundant row in the other of the sub-arrays that is arranged in an order complementary to that of the activated redundant row. By activating a redundant row in one sub-array and disabling the corresponding redundant row in an adjacent sub-array, the architecture allows for repairs to be conducted in the one sub-array while a good row in the adjacent sub-array is allowed to continue in operation. Also, since the redundant row used for repairs in the one sub-array is typically nearest the center of the sub-array, the disabled redundant row in the adjacent sub-array is nearest the edge of that sub-array, because it is arranged in an order complementary to that of the redundant row used for repairs. As a result, the disabled redundant row acts as an edge buffer between the primary and redundant rows of the adjacent sub-array and peripheral circuitry.

US Patent:

63108046, Oct 30, 2001

Filed:

Aug 16, 2000

Appl. No.:

9/639875

Inventors:

William K. Waller - Garland TX
Huy T. Vo - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 700

US Classification:

365200

Abstract:

A redundancy architecture for repairing a DRAM includes fuse banks for storing the row addresses of defective rows in sub-arrays of the DRAM. Row decoders activate a redundant row in one of the sub-arrays in response to receiving a row address matching one of the stored defective row addresses and, at the same time, disable a redundant row in the other of the sub-arrays that is arranged in an order complementary to that of the activated redundant row. By activating a redundant row in one sub-array and disabling the corresponding redundant row in an adjacent sub-array, the architecture allows for repairs to be conducted in the one sub-array while a good row in the adjacent sub-array is allowed to continue in operation. Also, since the redundant row used for repairs in the one sub-array is typically nearest the center of the sub-array, the disabled redundant row in the adjacent sub-array is nearest the edge of that sub-array, because it is arranged in an order complementary to that of the redundant row used for repairs. As a result, the disabled redundant row acts as an edge buffer between the primary and redundant rows of the adjacent sub-array and peripheral circuitry.

US Patent:

61250678, Sep 26, 2000

Filed:

Sep 13, 1999

Appl. No.:

9/394994

Inventors:

William K. Waller - Garland TX
Huy T. Vo - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 700

US Classification:

365200

Abstract:

A redundancy architecture for repairing a DRAM includes fuse banks for storing the row addresses of defective rows in sub-arrays of the DRAM. Row decoders activate a redundant row in one of the sub-arrays in response to receiving a row address matching one of the stored defective row addresses and, at the same time, disable a redundant row in the other of the sub-arrays that is arranged in an order complementary to that of the activated redundant row. By activating a redundant row in one sub-array and disabling the corresponding redundant row in an adjacent sub-array, the architecture allows for repairs to be conducted in the one sub-array while a good row in the adjacent sub-array is allowed to continue in operation. Also, since the redundant row used for repairs in the one sub-array is typically nearest the center of the sub-array, the disabled redundant row in the adjacent sub-array is nearest the edge of that sub-array, because it is arranged in an order complementary to that of the redundant row used for repairs. As a result, the disabled redundant row acts as an edge buffer between the primary and redundant rows of the adjacent sub-array and peripheral circuitry.