Ilango Ganga from San Jose, CA

Techniques To Perform Forward Error Correction For An Electrical Backplane
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US Patent:

7676733, Mar 9, 2010
Filed:

Jan 4, 2006
Appl. No.:

11/325765
Inventors:

Ilango S. Ganga - Cupertino CA, US
Luke Chang - Aloha OR, US
Andrey Belogolovy - St. Petersburg, RU
Andrei Ovchinnikov - St. Petersburg, RU
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

H03M 13/00
US Classification:

714775, 714776, 714789, 714821
Abstract:

Techniques to perform forward error correction for an electrical backplane are described. An apparatus comprises a physical layer unit having a forward error correction sublayer to perform forward error correction using a single bit to represent a two bit synchronization header.

Techniques To Perform Forward Error Correction For An Electrical Backplane
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US Patent:

7873892, Jan 18, 2011
Filed:

Dec 16, 2009
Appl. No.:

12/639797
Inventors:

Ilango S. Ganga - Cupertino CA, US
Luke Chang - Aloha OR, US
Andrey Belogolovy - St. Petersberg, RU
Andrei Ovchinnikov - St. Petersberg, RU
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

H03M 13/00
US Classification:

714752, 714786, 714799, 714 4
Abstract:

Techniques to perform forward error correction for an electrical backplane are described. An apparatus comprises a physical layer unit having a forward error correction sublayer to perform forward error correction using a single bit to represent a two bit synchronization header.

Techniques To Perform Forward Error Correction For An Electrical Backplane
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US Patent:

8108756, Jan 31, 2012
Filed:

Dec 9, 2010
Appl. No.:

12/964271
Inventors:

Ilango S. Ganga - Cupertino CA, US
Luke Chang - Aloha OR, US
Andrey Belogolovy - St. Petersburg, RU
Andrei Ovchinnikov - St. Petersburg, RU
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

H03M 13/00
US Classification:

714775, 714789
Abstract:

Techniques to perform forward error correction for an electrical backplane are described. An apparatus comprises a physical layer unit having a forward error correction sublayer to perform forward error correction using a single bit to represent a two bit synchronization header.

Interconnection Techniques
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US Patent:

8307265, Nov 6, 2012
Filed:

Mar 9, 2009
Appl. No.:

12/381205
Inventors:

Ilango Ganga - Cupertino CA, US
Richard Mellitz - Prosperity SC, US
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

H03M 13/00
US Classification:

714776, 714752, 370470, 370510, 370536
Abstract:

Techniques are described that can be used to extend the data transmission rate specified by 10GBASE-KR of IEEE 802. 3ap (2007) to more than 10 Gb/s using a multiple lane backplane. A signal for transmission over 10 Gb/s can be divided into multiple streams for transmission over multiple lanes. Multiple transceiver pairs can be used for transmission and receipt of the multiple streams. Each transceiver pair may comply with 10GBASE-KR of IEEE 802. 3ap (2007).

Techniques To Perform Forward Error Correction For An Electrical Backplane
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US Patent:

8352828, Jan 8, 2013
Filed:

Jan 11, 2012
Appl. No.:

13/348341
Inventors:

Ilango S. Ganga - Cupertino CA, US
Luke Chang - Aloha OR, US
Andrey Belogolovy - St. Petersburg, RU
Andrei Ovchinnikov - St. Petersburg, RU
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

H03M 13/00
US Classification:

714752, 714799
Abstract:

Techniques to perform forward error correction for an electrical backplane are described. An apparatus may include a physical layer unit having a forward error correction sublayer to perform forward error correction.

Enabling Functional Dependency In A Multi-Function Device
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US Patent:

8359408, Jan 22, 2013
Filed:

Jun 30, 2008
Appl. No.:

12/215995
Inventors:

Ilango S. Ganga - Cupertino CA, US
Manoj K. Wadekar - San Jose CA, US
Eric J. DeHaemer - Shrewsbury MA, US
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

G06F 3/00
US Classification:

710 10, 710 1, 710 3, 710 33, 711 2, 711111, 711117
Abstract:

In one embodiment, the present invention includes a method for reading configuration information from a multi-function device (MFD), building a dependency tree of a functional dependency of functions performed by the MFD based on the configuration information, which indicates that the MFD is capable of performing at least one function dependent upon another function, and loading software associated with the functions in order based at least in part on the indicated functional dependency. Other embodiments are described and claimed.

Cable Interconnection Techniques
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US Patent:

8370704, Feb 5, 2013
Filed:

Mar 9, 2009
Appl. No.:

12/381194
Inventors:

Ilango S. Ganga - Cupertino CA, US
Richard I. Mellitz - Prosperity SC, US
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

H03M 13/00
US Classification:

714757, 714775
Abstract:

Techniques are described that can extend the transmission rate over cable. Multiple cables can be used to increase the transmission rate. The transmission standard applied for each cable can be an Ethernet backplane standard such as IEEE 802. 3ap (2007). Data can be assigned to virtual lanes prior to transmission over a cable. Forward error correction may be applied to each virtual lane prior to transmission over cable. Forward error correction may be negotiated over a single virtual lane and then applied to all virtual lanes.

Interconnection Techniques
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US Patent:

8645804, Feb 4, 2014
Filed:

Oct 8, 2012
Appl. No.:

13/646872
Inventors:

Ilango Ganga - Cupertino CA, US
Richard Mellitz - Prosperity SC, US
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

H03M 13/00
US Classification:

714776, 714752, 370470, 370510, 370536
Abstract:

Techniques are described that can be used to extend the data transmission rate specified by 10GBASE-KR of IEEE 802. 3ap (2007) to more than 10 Gb/s using a multiple lane backplane. A signal for transmission over 10 Gb/s can be divided into multiple streams for transmission over multiple lanes. Multiple transceiver pairs can be used for transmission and receipt of the multiple streams. Each transceiver pair may comply with 10GBASE-KR of IEEE 802. 3ap (2007).