Jack C Peng

US Patent:

6650143, Nov 18, 2003

Filed:

Jul 8, 2002

Appl. No.:

10/191888

Inventors:

Jack Zezhong Peng - San Jose CA

Assignee:

Kilopass Technologies, Inc. - Sunnyvale CA

International Classification:

H03K 19094

US Classification:

326 44, 326 39, 326 41, 326 49

Abstract:

A field programmable gate array (FPGA) cell useful in a FPGA array having column bitlines, read bitlines, and row wordlines is disclosed. The cell comprises a capacitor having a first terminal and a second terminal, the first terminal connected to a column bitline, said second terminal connected to a switch control node, the capacitor having a dielectric between the first and second terminal. The cell also includes a select transistor having a gate, a source, and a drain, the gate connected to the read bitline, the source connected to the switch control node, and the drain connected to a row wordline. Finally, the cell includes a switch being controlled by the switch control node.

US Patent:

6667902, Dec 23, 2003

Filed:

Dec 17, 2001

Appl. No.:

10/024327

Inventors:

Jack Zezhong Peng - San Jose CA

Assignee:

Kilopass Technologies, Inc. - Sunnyvale CA

International Classification:

G11C 1134

US Classification:

365182, 365 94, 365103, 365104, 36518518, 36518911, 365226, 257 69, 257204, 257321

Abstract:

A semiconductor memory cell having a data storage element constructed around an ultra-thin dielectric, such as a gate oxide, is used to store information by stressing the ultra-thin dielectric into breakdown (soft or hard breakdown) to set the leakage current level of the memory cell. The memory cell is read by sensing the current drawn by the cell. A suitable ultra-thin dielectric is high quality gate oxide of about 50 thickness or less, as commonly available from presently available advanced CMOS logic processes.

US Patent:

6671040, Dec 30, 2003

Filed:

Sep 26, 2002

Appl. No.:

10/256483

Inventors:

David Fong - Cupertino CA
Fei Ye - Cupertino CA
Jack Zezhong Peng - San Jose CA

Assignee:

Kilopass Technologies, Inc. - Sunnyvale CA

International Classification:

G11C 1604

US Classification:

35618908, 36518909, 36518911

Abstract:

A programming circuit includes a wordline decoder, an adjustable voltage generator, and a column transistor. The programming circuit is useful in programming a memory cell comprised of a select transistor and a data storage element. The data storage element is programmed by a programming current. The amount of the programming current can be modulated by the column transistor, the select transistor, or the adjustable voltage generator.

US Patent:

6700151, Mar 2, 2004

Filed:

Oct 17, 2001

Appl. No.:

09/982314

Inventors:

Jack Zezhong Peng - San Jose CA

Assignee:

Kilopass Technologies, Inc. - Sunnyvale CA

International Classification:

H01L 27108

US Classification:

257298, 257296, 257302, 257314, 257321, 257253, 257328, 438253, 438259, 438300, 438156

Abstract:

A reprogrammable non-volatile memory array and constituent memory cells is disclosed. The semiconductor memory cells each have a data storage element constructed around an ultra-thin dielectric, such as a gate oxide. The gate oxide is used to store information by stressing the ultra-thin dielectric into breakdown (soft or hard breakdown) to set the leakage current level of the memory cell. The memory cell is read by sensing the current drawn by the cell. A suitable ultra-thin dielectric is high quality gate oxide of about 50 thickness or less, as commonly available from presently available advanced CMOS logic processes. The memory cells are first programmed by stressing the gate oxide until soft breakdown occurs. The memory cells are then subsequently reprogrammed by increasing the breakdown of the gate oxide.

US Patent:

6766960, Jul 27, 2004

Filed:

Oct 17, 2001

Appl. No.:

09/982034

Inventors:

Jack Zezhong Peng - San Jose CA

Assignee:

Kilopass Technologies, Inc. - Sunnyvale CA

International Classification:

G06K 1906

US Classification:

235492, 257351, 257357, 257296, 257298, 365 52, 36518529

Abstract:

A smart card having improved non-volatile memory and a processor. The memory includes of a plurality of memory cells. The semiconductor memory cells each have a data storage element constructed around an ultra-thin dielectric, such as gate oxide. The gate oxide is used to store information by stressing the ultra-thin dielectric into breakdown (soft or hard breakdown) to set the leakage current level of the memory cell. The memory cell is read be sensing the current drawn by the cell. A suitable ultra-thin dielectric is high quality gate oxide of about 50 angstroms thickness or less, as commonly available from presently available advance CMOS logic process.

US Patent:

6777757, Aug 17, 2004

Filed:

Apr 26, 2002

Appl. No.:

10/133704

Inventors:

Jack Zezhong Peng - San Jose CA
David Fong - Cupertino CA

Assignee:

Kilopass Technologies, Inc. - Sunnyvale CA

International Classification:

H01L 2994

US Classification:

257368, 257390, 257E2708, 257 5, 365177, 365178

Abstract:

A programmable memory cell comprised of a transistor located at the crosspoint of a column bitline and a row wordline is disclosed. The transistor has its gate formed from the column bitline and its source connected to the row wordline. The memory cell is programmed by applying a voltage potential between the column bitline and the row wordline to produce a programmed n+ region in the substrate underlying the gate of the transistor.

US Patent:

6791891, Sep 14, 2004

Filed:

Apr 2, 2003

Appl. No.:

10/406406

Inventors:

Jack Zezhong Peng - San Jose CA
Harry Shengwen Luan - Saratoga CA
Jianguo Wang - Cupertino CA
Zhongshan Liu - Plano TX
David Fong - Cupertino CA
Fei Ye - Cupertino CA

Assignee:

Kilopass Technologies, Inc. - Sunnyvale CA

International Classification:

G11C 700

US Classification:

365201, 365149

Abstract:

A method of testing a memory cell is disclosed. The memory cell has a data storage element constructed around an ultra-thin dielectric, such as a gate oxide, which is used to store information by stressing the ultra-thin dielectric into breakdown (soft or hard breakdown) to set the leakage current level of the memory cell. In order to ensure that the gate oxide underlying the data storage elements are of sufficient quality for programming, the memory cells of a memory array may be tested by applying a voltage across the gate oxide of the data storage element and measuring the current flow. Resultant current flow outside of a predetermined range indicates a defective memory cell.

US Patent:

6798693, Sep 28, 2004

Filed:

Sep 18, 2001

Appl. No.:

09/955641

Inventors:

Jack Zezhong Peng - San Jose CA

Assignee:

Kilopass Technologies, Inc. - Sunnyvale CA

International Classification:

G11C 1134

US Classification:

365177, 257296, 257298

Abstract:

A semiconductor memory cell having a data storage element constructed around an ultra-thin dielectric, such as a gate oxide, is used to store information by stressing the ultra-thin dielectric into breakdown (soft or hard breakdown) to set the leakage current level of the memory cell. The memory cell is read by sensing the current drawn by the cell. A suitable ultra-thin dielectric is high quality gate oxide of about 50 thickness or less, as commonly available from presently available advanced CMOS logic processes.