James R Comfort

US Patent:

57576122, May 26, 1998

Filed:

Apr 23, 1996

Appl. No.:

8/636624

Inventors:

Raul Edmundo Acosta - White Plains NY
James Hartfiel Comfort - New City NY
Alfred Grill - White Plains NY
David Edward Kotecki - Hopewell Junction NY
Katherine Lynn Saenger - Ossining NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01G 406

US Classification:

3613214

Abstract:

Structures for memory cell applications, including capacitors for DRAM and ferroelectric memory cells from FRAM, whose method of manufacture consists of depositing a ferroelectric or high-epsilon dielectric material to completely fill a cavity whose geometrical width is the sole determinant of the thickness of the electrically active portion of the ferroelectric or high-epsilon dielectric layer in the final device. In the preferred embodiment, the cavity into which the dielectric is deposited is defined by the gap between the plate and stack electrodes which are deposited and patterned in a through-mask plating step prior to the dielectric deposition.

US Patent:

62423215, Jun 5, 2001

Filed:

May 3, 1999

Appl. No.:

9/303595

Inventors:

Raul Edmundo Acosta - White Plains NY
James Hartfiel Comfort - New City NY
Alfred Grill - White Plains NY
David Edward Kotecki - Hopewell Junction NY
Katherine Lynn Saenger - Ossining NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2176

US Classification:

438424

Abstract:

Structures for memory cell applications, including capacitors for DRAM and ferroelectric memory cells from FRAM, whose method of manufacture consists of depositing a ferroelectric or high-epsilon dielectric material to completely fill a cavity whose geometrical width is the sole determinant of the thickness of the electrically active portion of the ferroelectric or high-epsilon dielectric layer in the final device. In the preferred embodiment, the cavity into which the dielectric is deposited is defined by the gap between the plate and stack electrodes which are deposited and patterned in a through-mask plating step prior to the dielectric deposition.