Jared W Stark

US Patent:

7143272, Nov 28, 2006

Filed:

Dec 27, 2002

Appl. No.:

10/330492

Inventors:

Chris B. Wilkerson - Portland OR, US
Jared W. Stark - Portland OR, US
Renju Thomas - College Park MD, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 9/44

US Classification:

712240

Abstract:

Associated with an instruction in a program is a computation history. The computation history represents all objects that affect the result of the instruction, such objects including (but not limited to) registers, memory locations, static values, and instruction program counters. The computation history may be used to make a prediction about a property of the instruction.

US Patent:

7380111, May 27, 2008

Filed:

Jul 8, 2004

Appl. No.:

10/888052

Inventors:

Edward T. Grochowski - San Jose CA, US
Jared W. Stark - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 9/38

US Classification:

712239, 711155

Abstract:

A method for processing registers in an out-of-order processor. A predicate in an instruction is predicted. An architecturally correct value is then computed using a read-modify-write operation. The predicted value is compared to the architecturally correct value. The instruction with an incorrectly-predicted predicate is flushed from the pipeline if the predicted value and the architecturally correct value are different.

US Patent:

7624258, Nov 24, 2009

Filed:

Oct 18, 2006

Appl. No.:

11/550747

Inventors:

Chris B. Wilkerson - Portland OR, US
Jared W. Stark - Portland OR, US
Renju Thomas - College Park MD, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 9/00

US Classification:

712240

Abstract:

Associated with an instruction in a program is a computation history. The computation history represents all objects that affect the result of the instruction, such objects including (but not limited to) registers, memory locations, static values, and instruction program counters. The computation history may be used to make a prediction about a property of the instruction.

US Patent:

20020188804, Dec 12, 2002

Filed:

Jun 12, 2001

Appl. No.:

09/881314

Inventors:

Ryan Rakvic - San Jose CA, US
John Shen - San Jose CA, US
Bohuslav Rychlik - Santa Clara CA, US
Christopher Wilkerson - Portland OR, US
Jared Stark - Portland OR, US
Hong Wang - Fremont CA, US

International Classification:

G06F012/00

US Classification:

711/118000, 711/154000

Abstract:

A load instruction is classified as vital or non-vital. One of a number of caches with different latencies is selected, based on a vitality of the load instruction. Data are then loaded through the selected cache into a register in a microprocessor.

US Patent:

20030126414, Jul 3, 2003

Filed:

Jan 2, 2002

Appl. No.:

10/038036

Inventors:

Edward Grochowski - San Jose CA, US
Jared Stark - Portland OR, US

International Classification:

G06F009/00

US Classification:

712/225000, 712/226000

Abstract:

A method for processing registers in an out-of-order processor. A predicate in an instruction is predicted. An architecturally correct value is then computed using a read-modify-write operation. The predicted value is compared to the architecturally correct value. The instruction with an incorrectly-predicted predicate is flushed from the pipeline if the predicted value and the architecturally correct value are different.

US Patent:

20030140216, Jul 24, 2003

Filed:

Jan 22, 2002

Appl. No.:

10/055483

Inventors:

Jared Stark - Portland OR, US
Mary Brown - Austin TX, US

International Classification:

G06F009/30

US Classification:

712/214000

Abstract:

A processor having select-free scheduling separates the wakeup and select logic into two loops. A wakeup loop holds scheduler instructions including unexecuted instructions, and indicates which of the unexecuted instructions that may be ready to be executed. At least one of the unexecuted instructions to wakeup and notify at least another of the unexecuted instructions to speculatively wakeup. A select loop selects at least one of the indicated ready instructions for execution.

US Patent:

20040128448, Jul 1, 2004

Filed:

Dec 31, 2002

Appl. No.:

10/331336

Inventors:

Jared Stark - Portland OR, US
Chris Wilkerson - Portland OR, US
Onur Mutlu - Austin TX, US

Assignee:

INTEL CORPORATION

International Classification:

G06F012/00

US Classification:

711/137000, 711/125000, 712/207000, 712/235000

Abstract:

Processor architectures, and in particular, processor architectures with a cache-like structure to enable memory communication during runahead execution. In accordance with an embodiment of the present invention, a system including a memory; and an out-of-order processor coupled to the memory. The out-of-order processor including at least one execution unit, at least one cache coupled to the at least one execution unit; at least one address source coupled to the at least one cache; and a runahead cache coupled to the at least one address source.

US Patent:

20040154011, Aug 5, 2004

Filed:

Apr 24, 2003

Appl. No.:

10/423633

Inventors:

Hong Wang - Fremont CA, US
Tor Aamodt - Toronto, CA
Pedro Marcuello - Barcelona, ES
Jared Stark - Portland OR, US
John Shen - San Jose CA, US
Antonio Gonzalez - Barcelona, ES
Per Hammarlund - Hillsboro OR, US
Gerolf Hoflehner - Santa Clara CA, US
Perry Wang - San Jose CA, US
Steve Liao - Palo Alto CA, US

International Classification:

G06F009/45
G06F009/44

US Classification:

717/158000, 717/119000, 717/149000

Abstract:

The latencies associated with retrieving instruction information for a main thread are decreased through the use of a simultaneous helper thread. The helper thread is a speculative prefetch thread to perform instruction prefetch and/or trace pre-build for the main thread.