Jason G Hart

US Patent:

6501302, Dec 31, 2002

Filed:

Oct 15, 2001

Appl. No.:

09/977770

Inventors:

Kyung T. Lee - Santa Clara CA
Jason M. Hart - Santa Clara CA

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G01R 1500

US Classification:

327 55, 327 57

Abstract:

A single-input/dual output sense amplifier includes cross-coupled transistors connected to a reference voltage; a first input transistor and a second input transistor connected to the cross-coupled transistors, wherein the first input transistor is coupled to a single input bit-line and the second input transistor is coupled to a reference voltage; an inverter receiving the input bit-line signal and outputting a complement of the input bit-line signal; a control circuit coupled to the second input transistor and receiving the complement of the input bit-line signal, wherein the cross-coupled transistors produce dual differential outputs. A method of producing dual differential output signals from a single input signal includes receiving a single input bit-line signal; inverting the received single input bit-line signal to produce the complement of the received single input bit-line signal; controlling the charging and discharging of a reference node based on the complement of the received input bit-line signal; and outputting dual differential output signals based on the single input bit-line signal and the reference node.

US Patent:

7791393, Sep 7, 2010

Filed:

Apr 8, 2009

Appl. No.:

12/420540

Inventors:

Robert P. Masleid - Monte Sereno CA, US
Heechoul Park - San Jose CA, US
Jason M. Hart - Hayden ID, US

Assignee:

Oracle America, Inc. - Redwood City CA

International Classification:

H03K 3/00

US Classification:

327291, 327295, 327174, 327415

Abstract:

A clock generating circuit includes a source clock, a first clock generated from the source clock through a first header, a second clock generated from the source clock through a second header and an inverter, wherein the second clock is out of phase with respect to the first clock, a first delayed falling edge clock, wherein the first delayed falling edge clock corresponds to the first clock with a first delayed falling edge, and a second delayed falling edge clock, wherein the second delayed falling edge clock corresponds to the second clock with a second delayed falling edge. The first delayed falling edge clock is generated from a first leading edge path and a first falling edge path, both originating from the source clock, that are inputted to a first delay chain.

US Patent:

8181073, May 15, 2012

Filed:

Sep 23, 2009

Appl. No.:

12/565689

Inventors:

Ali Vahidsafa - Palo Alto CA, US
Robert P. Masleid - Monte Sereno CA, US
Jason M. Hart - Hayden ID, US
Zhirong Feng - San Jose CA, US

Assignee:

Oracle America, Inc. - Redwood City CA

International Classification:

G01R 31/28

US Classification:

714726, 714731, 714 30, 714718, 714729, 714733, 714734, 711104, 327202, 327208, 327199, 327216, 327218, 365201

Abstract:

A SRAM (Static Random Access Memory) macro test flop circuit includes a flip-flop circuit, a scan control circuit, and an output buffer circuit. The flip-flop circuit includes a master latch circuit and a slave latch circuit. The master latch circuit includes a master feed-back circuit including a master storage node and a master feed-forward circuit. The slave latch circuit includes a slave feed-back circuit including a slave storage node and a slave feed-forward circuit driven from the master latch. The scan control circuit includes a scan slave feed-forward circuit, a scan latch circuit, and a scan driver circuit driven by the scan feed-back circuit. The scan latch circuit includes a scan feed-back circuit comprising a scan storage node and a scan feed-forward circuit driven from the slave latch. The output buffer circuit includes a master driver driven from master latch circuit and a slave driver driven from slave latch circuit.

US Patent:

8381271, Feb 19, 2013

Filed:

Sep 19, 2006

Appl. No.:

11/523344

Inventors:

Timothy Dingwall - Wenniassa, AU
Matthew Herscovitch - Chapman, AU
Jason Hart - Fremont CA, US
John F. Clark - Orem UT, US
John Boyer - Ottawa, CA

Assignee:

Actividentity (Australia) Pty, Ltd. - Deakin, Act

International Classification:

G06F 7/04
G06F 17/30

US Classification:

726 5, 726 1, 726 2, 726 3, 726 4, 726 8, 726 9, 726 10, 726 18, 713165, 713183, 713193, 713194, 705 18, 705 42, 705 70

Abstract:

A method and system for providing remote user access to secure financial applications by deployment of SSO software () to client workstations (), including receiving a password for collaborating access to a secure server (); navigating to the secure server () using a web browser () on a remote workstation (); providing user authorization details and the received password to the secure server (); generating a subsequent password at the secure server () upon validation of the user authorization details and received password; downloading an SSO deployment file () to the remote workstation (), said deployment file () including the subsequent password; executing the SSO deployment file () to install an SSO client application () on the remote workstation; reading workstation settings and user credentials from a secure file or data store; and running the SSO client application () on the workstation to employ the user credentials and subsequent password to logon to the secure application.

US Patent:

8436668, May 7, 2013

Filed:

Jan 4, 2011

Appl. No.:

12/984174

Inventors:

Robert P. Masleid - Monte Sereno CA, US
Jason M. Hart - Hayden ID, US

Assignee:

Oracle International Corporation - Redwood City CA

International Classification:

H03K 3/356

US Classification:

327208, 327210, 327211, 327212, 327218, 326 93, 326 95, 326 98

Abstract:

A flop circuit is disclosed. The flop circuit includes an input circuit configured to hold a logic value of an input signal received on its input node. The flop circuit further includes a storage circuit configured to, responsive to a pulse clock transitioning to a first logic level, receive and store the logic value and a complement of the logic value. A transfer circuit is coupled between the input circuit and the storage circuit, wherein the transfer circuit is configured to transfer the logic value from the input circuit to the storage circuit responsive to the pulse clock transitioning to the first logic level. The transfer circuit includes a first float node and a second float node and is configured such that at least one of the float nodes is floating during a portion of the operational cycle of the flop circuit.

US Patent:

8628019, Jan 14, 2014

Filed:

Jan 3, 2008

Appl. No.:

11/969129

Inventors:

Yves Louis Gabriel Audebert - Los Gatos CA, US
Eric Fernand Le Saint - Cupertino CA, US
Jason Hart - Fremont CA, US
Dominique Fedronic - Belmont CA, US

Assignee:

ActivIdentity, Inc. - Fremont CA

International Classification:

G06F 17/00
G06K 19/00
G06K 19/06
G05B 19/00

US Classification:

235492, 235375, 235382, 235487, 340 52, 340 57, 340 58, 3405721

Abstract:

A portable authentication system includes a security module, that may be a smart card, SIM (Subscriber Identity Module), USB controller with a secure chip, or similar module capable of storing one or more credentials, and an interface module such as a digital badge holder that is able to communicate with the security module, for instance by providing a smart card communication interface. The portable authentication system may be either a single integrated system or a dual system where the security module can be removed or disconnected from the interface system.

US Patent:

20120096909, Apr 26, 2012

Filed:

May 3, 2010

Appl. No.:

13/318526

Inventors:

Jason Hart - Fremont CA, US
Matthew Herscovitch - Fremont CA, US
Sotoudeh Hamedi Hagh - Fremont CA, US

International Classification:

E05B 49/02
G08B 29/00
E05B 47/00

US Classification:

702781, 70280, 340 56

Abstract:

The present invention provides an electronic locking system and method that includes a lock with a locking member and at least one antenna. A remote power source remotely powers the lock to actuate the locking member, using induction technology.

US Patent:

20130061303, Mar 7, 2013

Filed:

Feb 25, 2011

Appl. No.:

13/579233

Inventors:

Jason Dean Hart - Fremont CA, US
Matthew Patrick Herscovitch - Chapman, AU
Sooseok Oh - Fremont CA, US

Assignee:

IDONDEMAND, INC. - Fremont CA

International Classification:

G06F 21/00

US Classification:

726 6

Abstract:

A method of providing continuous authentication in a contactless environment is provided. The method includes providing a reader having a contactless interface, as well as a device, operable to communicate with the reader. The method further includes the steps of receiving at the reader a first authentication request from the device, and communicating from the reader a second authentication request to a secure transaction service. The secure transaction service holds authentication credentials relating to the device. Authentication credentials relating to the device are received at the reader from the secure transaction service, and the reader provides continuous authentication based at least in part on the authentication credentials received from the secure transaction service.