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Jed H Rankin

age ~48

from Richmond, VT

Also known as:
  • Jed Rankin
  • Darcie Rankin
  • Jed Kankin
  • Jed E
Phone and address:
2552 Stage Rd, Richmond, VT 05477
(802)4345832

Jed Rankin Phones & Addresses

  • 2552 Stage Rd, Richmond, VT 05477 • (802)4345832
  • 211 Juniper Dr, South Burlington, VT 05403 • (802)8599221
  • Burlington, VT
  • Essex, VT
  • Potsdam, NY

Work

  • Position:
    Professional/Technical

Education

  • Degree:
    Graduate or professional degree

Resumes

Jed Rankin Photo 1

Spie Bacus Photomask Cochair

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Location:
1050 east Arques Ave, Sunnyvale, CA 94085
Industry:
Semiconductors
Work:
Spie
Spie Bacus Photomask Cochair

Globalfoundries
Distinguished Senior Member of the Technical Staff, Worldwide Photomask Development Strategy

Ibm Jul 2014 - Jun 2015
Senior Technical Staff Member, Euv Photomask Development and Program Management

Ibm Jun 2014 - Jun 2015
Senior Technical Staff Member, Photomask Development and Manufacture

Ibm Mar 2009 - 2011
Senior Mask Development Engineer
Education:
Clarkson University 1992 - 1995
Bachelors, Bachelor of Science, Chemical Engineering
St Johnsbury Academy 1988 - 1992
University of Phoenix
Master of Business Administration, Masters, Business
Skills:
Semiconductors
Cross Functional Team Leadership
Integration
Cmos
Characterization
Process Integration
Manufacturing
Ic
Design of Experiments
Lean Manufacturing
Process Simulation
Project Management
Strategic Planning
Patents
Semiconductor Industry
Testing
Process Engineering
Failure Analysis
Eda
Competitive Analysis
Asic
Simulations
Electronics
Business Development
Semiconductor Process
Thin Films
Engineering
R&D
Six Sigma
Technology Transfer
Intellectual Property
It Strategy
Engineering Management
Spc
Debugging
Soc
Patentability
Technical Project Management
Semiconductor Process Integration
Photomask Process Development
Intellectual Property Development
Organizational Strategy Development
Systems and Software Planning
Light Software Development
Reverse Engineering
Management
Organizational Development
Strategy
Mentoring
Technical Leadership
Interests:
Children
Trail Running
Hikingfavorite Activity
Playing With My Kids
Economic Empowerment
Outdoor Activities
Education
Including Backcountry Telemarking
Cycling
Hiking Favorite Activity
Science and Technology
Disaster and Humanitarian Relief
Languages:
Japanese
Jed Rankin Photo 2

Jed Rankin

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Us Patents

  • Buried Butted Contact And Method For Fabricating

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  • US Patent:
    6335272, Jan 1, 2002
  • Filed:
    Aug 14, 2000
  • Appl. No.:
    09/637935
  • Inventors:
    Archibald Allen - Shelburne VT
    Jerome B. Lasky - Essex Junction VT
    Randy W. Mann - Jericho VT
    Jed H. Rankin - Burlington VT
    Francis R. White - Essex Junction VT
  • Assignee:
    International Business Machines Corporation - Armonk NY
  • International Classification:
    H01L 214763
  • US Classification:
    438621, 438620, 257773, 257372
  • Abstract:
    A buried butted contact and method for its fabrication are provided which includes a substrate having dopants of a first conductivity type and having shallow trench isolation. Dopants of a second conductivity type are located in the bottom of an opening in said substrate. Ohmic contact is provided between the dopants in the substrate and the low diffusivity dopants that is located on a side wall of the opening. The contact is a metal silicide, metal and/or metal alloy.
  • Mask With Linewidth Compensation And Method Of Making Same

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  • US Patent:
    6338921, Jan 15, 2002
  • Filed:
    Jan 7, 2000
  • Appl. No.:
    09/479150
  • Inventors:
    James A. Bruce - Williston VT
    David V. Horak - Essex Junction VT
    Randy W. Mann - Jericho VT
    Jed H. Rankin - Burlington VT
    Andrew J. Watts - Essex VT
  • Assignee:
    International Business Machines Corporation - Armonk NY
  • International Classification:
    G03F 102
  • US Classification:
    430 5, 430323, 430327, 216 12, 216 46
  • Abstract:
    A mask ( ) with linewidth compensation and a method of making same. The mask provides for optimized imaging of isolated patterns ( ) and nested patterns ( ) present on the same mask. The compensated mask is formed from an uncompensated mask ( ) and comprises an upper surface ( ) upon which the isolated and nested patterns are formed. The isolated pattern comprises a first segment ( ) having first sidewalls ( S). The nested pattern comprises second segments ( ) proximate each other and having second sidewalls ( S). A partial conformal layer ( ) covers the first segment and has feet ( ) outwardly extending a distance d from the first sidewalls along the upper surface. The feet are preferably of a thickness that partially transmits exposure light.
  • Method For Eliminating Transfer Gate Sacrificial Oxide

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  • US Patent:
    6342431, Jan 29, 2002
  • Filed:
    Oct 14, 1998
  • Appl. No.:
    09/173089
  • Inventors:
    Kevin M. Houlihan - Burlington VT
    Jed H. Rankin - Burlington VT
  • Assignee:
    International Business Machines Corporation - Armonk NY
  • International Classification:
    H01L 218238
  • US Classification:
    438433, 438294, 438297, 438296, 438449
  • Abstract:
    A method of forming a semiconductor device, includes forming a layer of oxide on a semiconductor substrate, forming a layer of silicon nitride on the oxide layer, forming isolation regions in the substrate using the oxide layer and the nitride layer, removing the silicon nitride layer, ion implanting dopant ions using the original oxide layer as a screen, into the substrate, and removing the oxide layer and forming a gate oxide layer over the substrate. Another method of forming an active area of a semiconductor device, includes using a pad oxide, remaining after removing a film layer thereover of an oxide/film mask stack, for a screen layer for well implants formed in the substrate, removing the oxide layer and forming a gate oxide over the substrate, following defining the well implants, without using a sacrificial oxide.
  • Diode With Alterable Conductivity And Method Of Making Same

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  • US Patent:
    6344679, Feb 5, 2002
  • Filed:
    Nov 19, 1999
  • Appl. No.:
    09/443524
  • Inventors:
    William A. Klaasen - Underhill VT
    Wilbur D. Pricer - Charlotte VT
    Jed Hickory Rankin - Burlington VT
  • Assignee:
    International Business Machines Corporation - Armonk NY
  • International Classification:
    G11C 1706
  • US Classification:
    257594, 257428, 257529, 257530, 365 96
  • Abstract:
    A semiconductor device ( ) having a plurality of diodes ( ) with alterable electrical conductivity by a source of energy ( ), e. g. , a laser, external to the semiconductor device. The diodes are formed and energy is applied to alter the electrical conductivity at least 10%, and preferably by several orders of magnitude. Certain embodiments ( and ) are formed so as to function as anti-fuses, while another embodiment ( ) functions as a fuse. The diodes may be formed as planar diodes ( and ) or as lateral diodes ( ).
  • Raised Wall Isolation Device With Spacer Isolated Contacts And The Method Of So Forming

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  • US Patent:
    6380063, Apr 30, 2002
  • Filed:
    Mar 1, 2000
  • Appl. No.:
    09/516697
  • Inventors:
    Juan A. Chediak - Berkeley CA
    Thomas G. Ference - Essex Junction VT
    Kurt R. Kimmel - Jericho VT
    Alain Loiseau - Williston VT
    Randy W. Mann - Jericho VT
    Jed H. Rankin - Burlington VT
  • Assignee:
    International Business Machines Corporation - Armonk NY
  • International Classification:
    H01L 214763
  • US Classification:
    438621, 438221, 438296, 438424, 438620, 438655
  • Abstract:
    A semiconductor device having borderless contacts thereby providing a device having a reduced overall size. In particular, the device includes a plurality of shallow trench isolations and a plurality of dielectric isolations thereon to separate the adjoining device components and prevent shorts. Sidewall spacers surrounding and extend slightly above the device gates and dielectric isolations to further prevent shorts. A layer of conductive material atop each gate and diffusion region provides for coplanar contact surfaces. A layer of silicide beneath select regions of the conductive layer enhance electrical conductivity within the device. An internal wireless interconnection to electrically connect diffusion regions of different logic devices within the structure is also provided.
  • Method Of Forming Resist Images By Periodic Pattern Removal

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  • US Patent:
    6387596, May 14, 2002
  • Filed:
    Aug 30, 1999
  • Appl. No.:
    09/385929
  • Inventors:
    Daniel C. Cole - Jericho VT
    Edward W. Conrad - Jeffersonville VT
    David V. Horak - Essex Junction VT
    Randy W. Mann - Jericho VT
    Paul W. Pastel - Essex Junction VT
    Jed H. Rankin - Burlington VT
    Andrew J. Watts - Essex Junction VT
  • Assignee:
    International Business Machines Corporation - Armonk NY
  • International Classification:
    G03F 720
  • US Classification:
    430311, 430 5, 430312
  • Abstract:
    The present invention provides a method of forming nested and isolated images in a photosensitive resist. In the disclosed method, the entire surface of the photosensitive resist or selected regions thereof is exposed to a first mask having a set of nested, i. e. repeating pattern or grid images thereon, and then exposed to a second mask in order to remove unwanted portions of the nested image, so as to provide regions of nested and regions of isolated images in said photosensitive resist. The method may also be used to form regions having images in proximity to one another and regions having isolated images by exposing the entire surface of the photosensitive resist to a first mask having repeating patterns, and then removing entire or portions of the repeating patterns by exposure of the photosensitive resist with a second mask.
  • Fabricating A Square Spacer

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  • US Patent:
    6426524, Jul 30, 2002
  • Filed:
    Oct 18, 2000
  • Appl. No.:
    09/691547
  • Inventors:
    Chung Hon Lam - Williston VT
    Jed Hickory Rankin - Burlington VT
    Christa Regina Willets - Jericho VT
    Arthur Paul Johnson - Essex Junction VT
  • Assignee:
    International Business Machines Corporation - Armonk NY
  • International Classification:
    H01L 27108
  • US Classification:
    257296, 257309, 257328, 257329, 257330, 257331, 257332, 438303, 438305
  • Abstract:
    A square spacer and method of fabrication. The method includes forming a spacer film on a mandrel positioned on a substrate, forming an oxide film on the spacer film, performing a first etching, and performing a second etching. The spacer film is formed on perpendicular first and second sides of the mandrel. A first region and a second region of the spacer film are on the first side and the second side of the mandrel, respectively. The spacer film may include a conductive material such as polysilicon or tungsten. The spacer film may alternatively include an insulative material such as silicon dioxide, silicon nitride, or silicon oxynitride. The oxide film is formed such that a first region and a second region of the oxide film are on the first region and the second region of the spacer film, respectively. The oxide film may include silicon dioxide. The first etching etches away the first region of the oxide film and a portion of the first region of the spacer film.
  • Method And Structure For A Semiconductor Fuse

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  • US Patent:
    6440834, Aug 27, 2002
  • Filed:
    Apr 6, 2001
  • Appl. No.:
    09/827871
  • Inventors:
    Timothy Harrison Daubenspeck - Colchester VT
    William Thomas Motsiff - Essex Junction VT
    Jed Hickory Rankin - Burlington VT
  • Assignee:
    International Business Machines Corporation - Armonk NY
  • International Classification:
    H01L 2144
  • US Classification:
    438601, 438132, 438600, 257529
  • Abstract:
    A semiconductor fuse structure having a conductive fuse material abutting a first and second conductive line is provided. The fuse of the present invention does not substantially damage the surrounding semiconductor material therefore it can be used with a wide variety of materials including porous, mechanically fragile, low dielectric constant materials and high conductive metals like Cu. Methods of fabricating such a semiconductor fuse structure are also provided herein.

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Jed Rankin Photo 3

Jed Rankin

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Friends:
Ron Segars, Jaime Rankin Stone, Gail Carter, Jeff Craig, Debbie Terrell
Jed Rankin Photo 4

Jed Rankin

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Classmates

Jed Rankin Photo 5

Jed Rankin Mari NC Clas...

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Jed Rankin 1978 graduate of McDowell High School in Marion, NC is on Classmates.com. See pictures, plan your class reunion and get caught up with Jed and other high school alumni.

Googleplus

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Jed Rankin

Youtube

State Champion Canadian Wildcats Defensive Hi...

Just a few highlights from the State Champion Canadian Wildcats "D". L...

  • Category:
    Sports
  • Uploaded:
    11 Feb, 2008
  • Duration:
    3m 4s

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