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Jed H Rankin

age ~45

from Richmond, VT

Also known as:
  • Darcie J Rankin
  • Jed H Kankin
  • J Rankin
2552 Stage Rd, Richmond, VT 05477(802)4345832

Jed Rankin Phones & Addresses

  • 2552 Stage Rd, Richmond, VT 05477 • (802)4345832
  • Burlington, VT
  • Essex Junction, VT
  • Potsdam, NY

Work

  • Position:
    Professional/Technical

Education

  • Degree:
    Graduate or professional degree

Us Patents

  • Buried Butted Contact And Method For Fabricating

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  • US Patent:
    6335272, Jan 1, 2002
  • Filed:
    Aug 14, 2000
  • Appl. No.:
    09/637935
  • Inventors:
    Archibald Allen - Shelburne VT
    Jerome B. Lasky - Essex Junction VT
    Randy W. Mann - Jericho VT
    Jed H. Rankin - Burlington VT
    Francis R. White - Essex Junction VT
  • Assignee:
    International Business Machines Corporation - Armonk NY
  • International Classification:
    H01L 214763
  • US Classification:
    438621, 438620, 257773, 257372
  • Abstract:
    A buried butted contact and method for its fabrication are provided which includes a substrate having dopants of a first conductivity type and having shallow trench isolation. Dopants of a second conductivity type are located in the bottom of an opening in said substrate. Ohmic contact is provided between the dopants in the substrate and the low diffusivity dopants that is located on a side wall of the opening. The contact is a metal silicide, metal and/or metal alloy.
  • Metal Gate Fet Having Reduced Threshold Voltage Roll-Off

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  • US Patent:
    8546252, Oct 1, 2013
  • Filed:
    Oct 5, 2009
  • Appl. No.:
    12/573440
  • Inventors:
    Brent A. Anderson - Jericho VT,
    Edward J. Nowak - Essex Junction VT,
    Jed H. Rankin - South Burlington VT,
  • Assignee:
    International Business Machines Corporation - Armonk NY
  • International Classification:
    H01L 29/72
  • US Classification:
    438592, 257E2119, 257E29255, 257288, 438183, 438199, 438270, 438275, 438561, 438587, 438595
  • Abstract:
    A structure and method to create a metal gate having reduced threshold voltage roll-off. A method includes: forming a gate dielectric material on a substrate; forming a gate electrode material on the gate dielectric material; and altering a first portion of the gate electrode material. The altering causes the first portion of the gate electrode material to have a first work function that is different than a second work function associated with a second portion of the gate electrode material.
  • Boundary Layer Formation And Resultant Structures

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  • US Patent:
    8465885, Jun 18, 2013
  • Filed:
    Feb 7, 2011
  • Appl. No.:
    13/021852
  • Inventors:
    Jed H. Rankin - Richmond VT,
  • Assignee:
    International Business Machines Corporation - Armonk NY
  • International Classification:
    G03F 1/68
  • US Classification:
    430 5
  • Abstract:
    A method for forming anti-boundary layer patterns includes patterning a first masking layer on a chrome layer, etching to remove portions of the chrome layer and expose portions of a first quartz layer, removing the first masking layer, patterning a second masking layer on portions of the chrome layer and the first quartz layer, and etching to remove exposed portions of the first quartz layer and to expose portions of an etch stop layer to define anti-boundary layers defined by the first quartz layer and the etch stop layer.
  • Structure, Method And System For Complementary Strain Fill For Integrated Circuit Chips

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  • US Patent:
    8470674, Jun 25, 2013
  • Filed:
    Jan 3, 2011
  • Appl. No.:
    12/983353
  • Inventors:
    Brent A. Anderson - Jericho VT,
    Edward J. Nowak - Essex Junction VT,
    Jed H. Rankin - Richmond VT,
  • Assignee:
    International Business Machines Corporation - Armonk NY
  • International Classification:
    H01L 21/8234
    H01L 27/118
  • US Classification:
    438275, 438199, 438228, 438238, 438279, 257206, 257274, 257336, 257351, 257369, 257E27062, 257E21611
  • Abstract:
    A structure, method and system for complementary strain fill for integrated circuit chips. The structure includes a first region of an integrated circuit having multiplicity of n-channel and p-channel field effect transistors (FETs); a first stressed layer over n-channel field effect transistors (NFETs) of the first region, the first stressed layer of a first stress type; a second stressed layer over p-channel field effect transistors (PFETs) of the first region, the second stressed layer of a second stress type, the second stress type opposite from the first stress type; and a second region of the integrated circuit, the second region not containing FETs, the second region containing first sub-regions of the first stressed layer and second sub-regions of the second stressed layer.
  • Methods And Structures For Increased Thermal Dissipation Of Thin Film Resistors

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  • US Patent:
    8470682, Jun 25, 2013
  • Filed:
    Dec 14, 2010
  • Appl. No.:
    12/968001
  • Inventors:
    Brent A. Anderson - Jericho VT,
    Jed H. Rankin - Richmond VT,
    Robert R. Robison - Colchester VT,
  • Assignee:
    International Business Machines Corporation - Armonk NY
  • International Classification:
    H01L 21/20
  • US Classification:
    438384, 257E21004, 438382
  • Abstract:
    A method of forming a semiconductor structure includes forming at least one trench in an insulator layer formed on a substrate. A distance between a bottom edge of the at least one trench and a top surface of a substrate is shorter than a distance between an uppermost surface of the insulator layer and the top surface of the substrate. The method also includes: forming a resistor on the insulator layer and extending into the at least one trench; forming a first contact in contact with the resistor; and forming a second contact in contact with the resistor such that current is configured to flow from the first contact to the second contact through a central portion of the resistor.
  • Nitride Etch For Improved Spacer Uniformity

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  • US Patent:
    8470713, Jun 25, 2013
  • Filed:
    Dec 13, 2010
  • Appl. No.:
    12/966432
  • Inventors:
    James A. Culp - Newburgh NY,
    John J. Ellis-Monaghan - Grand Isle VT,
    Jeffrey P. Gambino - Westford VT,
    Kirk D. Peterson - Jericho VT,
    Jed H. Rankin - Richmond VT,
    Christa R. Willets - Jericho VT,
  • Assignee:
    International Business Machines Corporation - Armonk NY
  • International Classification:
    H01L 21/311
  • US Classification:
    438695, 257E21249
  • Abstract:
    A method of forming dielectric spacers including providing a substrate comprising a first region having a first plurality of gate structures and a second region having a second plurality of gate structures and at least one oxide containing material or a carbon containing material. Forming a nitride containing layer over the first region having a thickness that is less than the thickness of the nitride containing layer that is present in the second region. Forming dielectric spacers from the nitride containing layer on the first plurality the second plurality of gate structures. The at least one oxide containing material or carbon containing material accelerates etching in the second region so that the thickness of the dielectric spacers in the first region is substantially equal to the thickness of the dielectric spacers in the second region of the substrate.
  • Micro-Electro-Mechanical System Tiltable Lens

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  • US Patent:
    8492807, Jul 23, 2013
  • Filed:
    Dec 7, 2009
  • Appl. No.:
    12/632040
  • Inventors:
    John J. Ellis-Monaghan - Grand Isle VT,
    Jeffrey P. Gambino - Westford VT,
    Kirk D. Peterson - Jericho VT,
    Jed H. Rankin - Richmond VT,
  • Assignee:
    International Business Machines Corporation - Armonk NY
  • International Classification:
    H01L 31/062
  • US Classification:
    257294, 257290, 257E31121
  • Abstract:
    A tiltable micro-electro-mechanical (MEMS) system lens comprises a microscopic lens located on a front surface of a semiconductor-on-insulator (SOI) substrate and a semiconductor rim surrounding the periphery of the microscopic lens. Two horizontal semiconductor beams located at different heights are provided within a top semiconductor layer. The microscopic lens may be tilted by applying an electrical bias between the lens rim and one of the two semiconductor beams, thereby altering the path of an optical beam through the microscopic lens. An array of tiltable microscopic lenses may be employed to form a composite lens having a variable focal length may be formed. A design structure for such a tiltable MEMS lens is also provided.
  • Fet Edram Trench Self-Aligned To Buried Strap

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  • US Patent:
    8492819, Jul 23, 2013
  • Filed:
    Jul 14, 2011
  • Appl. No.:
    13/182738
  • Inventors:
    Brent A. Anderson - Jericho VT,
    Edward J. Nowak - Essex Junction VT,
    Jed H. Rankin - Richmond VT,
  • Assignee:
    International Business Machines Corporation - Armonk NY
  • International Classification:
    H01L 27/06
    H01L 21/20
  • US Classification:
    257301, 257E29346, 257E21396, 438244
  • Abstract:
    A structure and method of making a field effect transistor (FET) embedded dynamic random access memory (eDRAM) cell array, which includes: a buried silicon strap extending into a buried oxide (BOX) layer of a silicon-on-insulator (SOI) substrate; a recessed trench capacitor extending down into the substrate layer of the SOI substrate; a lateral surface of a conductive top plate formed on the recessed trench capacitor that contacts a first lateral surface of the buried silicon strap; a dielectric cap disposed above the conductive top plate; a first FET formed from the silicon layer of the SOI substrate, in which a source/drain region of the first FET contacts a second lateral surface of the buried silicon strap; and a passing wordline disposed on a portion of the dielectric cap opposite to and separate from the buried silicon strap and connected to a gate of a second FET in an adjacent row of the FET eDRAM cell array.

Resumes

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Location:
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