Jeffrey Bruce Braun

US Patent:

7276419, Oct 2, 2007

Filed:

Oct 31, 2005

Appl. No.:

11/264068

Inventors:

Vishnu Khemka - Phoenix AZ, US
John M. Pigott - Phoenix AZ, US
Ronghua Zhu - Chandler AZ, US
Amitava Bose - Tempe AZ, US
Randall C. Gray - Tempe AZ, US
Jeffrey J. Braun - Tempe AZ, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 21/336

US Classification:

438305, 438306

Abstract:

A semiconductor device may include first, second, and third semiconductor layers. The first and third layers may have a first dopant type, and the second layer may have a second dopant type. A first region within the third semiconductor layer may have the second dopant type. A second region between the first region and the second semiconductor layer may have the first dopant type. A third region above the second region may have the first dopant type. A fourth semiconductor region adjacent to the third region may have a first concentration of the second dopant type. A source contact region may have a second concentration of the second dopant type adjacent to the third semiconductor region and adjacent to the fourth semiconductor region. The second concentration may be higher than the first concentration.

US Patent:

46985824, Oct 6, 1987

Filed:

Jul 23, 1986

Appl. No.:

6/889642

Inventors:

Jeffrey J. Braun - Chandler AZ
Kenneth M. Cook - Palatine IL

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G05F 1573

US Classification:

323285

Abstract:

A power driver having a power transistor (15) uses a disable unit (17) to disable the transistor (15) upon sensing a short circuit condition. No current sense resistors are used. The base-emitter voltage of the transistor (15) is compared by a comparator (14) with a reference signal provided by a reference signal unit (16) to determine the existence or absence of a short circuit condition. In the presence of a short circuit, the comparator (14) provides a fault detected signal to the disable unit (17). The disable unit functions to deny the control signal to the transistor (15) and to ground the base of the power transistor (15) to thereby doubly ensure disablement. In addition, the disable unit (17) has memory and will disable the transistor (15) until the control signal recycles.

US Patent:

51947609, Mar 16, 1993

Filed:

Dec 23, 1991

Appl. No.:

7/812444

Inventors:

Jeffrey J. Braun - Mesa AZ
Randall C. Gray - Tempe AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H03K 408
H03K 604

US Classification:

307263

Abstract:

A slew rate limited load driver is disclosed with a transistor switch (123) driving a load (125). The transistor switch (123) is controlled by a current from a current amplifier (107) and a current sink (111). The current amplifier (107) is driven from the combination of a source of compensating current (120) and a turn on current source (115). As a command signal (103) transitions, the source of compensating current (120) adds a transitional compensating current to the current derived from the turn on current source (115) and is amplified by the current amplifier (107). The output of the current amplifier (107) is combined with the output of the turn off current sink (111), to control the voltage slew rate to the load (101).

US Patent:

60520051, Apr 18, 2000

Filed:

Jan 21, 1997

Appl. No.:

8/787511

Inventors:

Jeffrey J. Braun - Tempe AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H03L 700

US Classification:

327143

Abstract:

A low current drain switch interface circuit includes an input terminal (105), coupled to a first terminal (201) of a diode (115). A voltage follower circuit (211) is coupled to a second terminal (203) of the diode (115). A current source (215) is coupled between an output terminal (213) of the voltage follower circuit (211) and a power supply terminal (111). A mechanical switch (101) is coupled to the input terminal (105). The voltage follower circuit (211) outputs a voltage (119) indicative of a physical state of the mechanical switch (101).

US Patent:

48795062, Nov 7, 1989

Filed:

Aug 2, 1988

Appl. No.:

7/227384

Inventors:

Jeffrey J. Braun - Mesa AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G05F 320

US Classification:

323314

Abstract:

A voltage supply circuit provides a desired regulated voltage at an output utilizing a PNP and an NPN current mirror arranged to oppose one another. The NPN current mirror includes a pair of transistors operated at different current densities which produce a delta V. sub. BE voltage that is used to produce a reference current. The reference current is used to derive the regulated voltage which is a function of two independent resistor ratios.

US Patent:

50103032, Apr 23, 1991

Filed:

Dec 8, 1989

Appl. No.:

7/447956

Inventors:

Jeffrey J. Braun - Mesa AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H03F 345

US Classification:

330257

Abstract:

Integrated circuit amplifier (10) implements unity voltage gain and its current gain is determined by the ratio of integrated circuit resistors (R1, R2). Amplifier input stage (Q1, Q2, Q4-Q7) has a pair of transistors (Q4, Q5) connected as a differential amplifier. An output transistor (Q13) connected to the collector of one (Q4) of the differential transistors amplifies the differential signal from the input stage and provides an output signal (at terminal 22). Current mirror circuitry (Q12, Q9) develops a current mirror signal (at 24) corresponding to current drawn through the output transistor (Q13). A load balancing circuit (Q8, Q3, R8) includes a transistor (Q3) having an input terminal directly connected to and loading the collector of another one (Q5) of the differential transistors. This configuration results in equal impedance and current loading for each of the collectors of the differential transistors (Q4, Q5). This minimizes any offset variation for the differential signal at the collector of one of the transistors (Q4) as a function of the conduction of the output stage tansistor (Q13).

US Patent:

52220117, Jun 22, 1993

Filed:

Nov 4, 1991

Appl. No.:

7/787443

Inventors:

Jeffrey J. Braun - Mesa AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01H 4732

US Classification:

361154

Abstract:

Load driver circuit (10) has first and second comparators (Cphd 1, C. sub. 2) which receive a load current signal (V. sub. s) indicative of current flowing through a load (11). The comparators provide, as output signals, set on and set off signals (at 21, 23) in response to comparing the load current signal (V. sub. s) with first and second thresholds (T. sub. 1, T. sub. 2). Driver circuitry (27, 43, 12) receives the set on and set off signals and provides a current control signal (at 18) for controlling load current. Preferably, disabling circuitry (30-34) disables the comparators (C. sub. 1, C. sub. 2) after and in response to the comparators providing their respective output signals (at 21, 23). Also, preferably enabling circuitry (40-42) enables the comparators (C. sub. 1, C. sub. 2) in response to comparing a sensed voltage (at 17), indicative of voltage at an output terminal of a switching device (12) that controls load current, with respect to a predetermined voltage (2. 5 volts).