Jeffrey John Sands

US Patent:

6584148, Jun 24, 2003

Filed:

Jun 2, 2000

Appl. No.:

09/586330

Inventors:

Brent R. Zitting - Harvest AL
Robert D. Deaton - Madison AL
Mark O. Rigby - Madison AL
Ron M. Roberson - Birmingham AL
Kevin R. Banks - Madison AL
Jeffrey J. Sands - Harvest AL

Assignee:

Nokia Inc. - Irving TX

International Classification:

H04M 124

US Classification:

375222, 379 2701, 379 2703, 379 2901, 379 3204

Abstract:

A system for testing a communication path for digital subscriber line (DSL) signals includes a loop management device coupled in the communication path between a DSL access multiplexer (DSLAM) and a DSL modem located at a customer premises. The system also includes a remote test interface coupled in the communication path between the loop management device and the DSL modem. The loop management device and the remote test interface communicate using voice-band signals transmitted over the communication path and collaboratively test the communication path.

US Patent:

56617631, Aug 26, 1997

Filed:

Jul 28, 1995

Appl. No.:

8/508589

Inventors:

Jeffrey J. Sands - Huntsville AL

Assignee:

Adtran, Inc. - Huntsville AL

International Classification:

H04L 700

US Classification:

375368

Abstract:

A programmable digital bit pattern detector detects the presence of a variable length, variable content M-bit serial bit pattern that is sequentially repeated in a digital bit stream during some prescribed time constraint, and indicates whether successive repetitions of the pattern satisfy a prescribed criterion, before declaring that the pattern has been successfully acquired. For this purpose, a variable length shift register is programmed with a copy of the pattern. During initial acquisition, in response to a match between a respective bit of the digital bit stream and the content of a selected stage of the shift register, the contents of the shift register are shifted by one bit stage; in response to a mismatch, clocking of the shift register is inhibited for that bit. Count signals are generated in association with successive pluralities of the M bits of the digital bit stream, and an "up/down" counter is incremented or decremented by the count signals, in accordance with whether successive bits of the digital bit stream match the copy of the bit pattern being clocked through the shift register. A maximum pattern match code representative of a prescribed bit error rate and time interval is programmed into a comparator and is compared with the contents of the "up/down" counter.

US Patent:

57578699, May 26, 1998

Filed:

Jul 28, 1995

Appl. No.:

8/508996

Inventors:

Jeffrey J. Sands - Huntsville AL
Michael D. Turner - Madison AL

Assignee:

ADTRAN, Inc. - Huntsville AL

International Classification:

H04L 700

US Classification:

375366

Abstract:

A frame sync acquisition mechanism accurately locates a frame synchronization word within successive selectively bit-stuffed frames of data by not only looking for the frame sync word in the two expected alternative frame sync word locations based upon either the addition of stuff bits or the lack of such stuff bits, but also selectively examining a pair of additional potential locations, one of which precedes and the other of which succeeds the two expected alternative frame sync word locations. If an exact match with the frame sync word is located in either of the expected locations, that location is selected as the reference for the next succeeding frame. During the search of the next successive frame and for every succeeding frame, an attempt is made to initially match the frame sync word with in either of these expected locations. If unable to do so, the search is expanded to encompass the entire window of location uncertainty, so as to include the two additional locations. During this expanded search, that location which yields the smallest number of bit errors is declared as the reference location for the next succeeding frame.