Jian Yang Huang

US Patent:

20230088701, Mar 23, 2023

Filed:

Jun 3, 2022

Appl. No.:

17/831617

Inventors:

- South San Francisco CA, US
Michael Joseph Mamounas - San Francisco CA, US
Jennifer Lee Schutzman - Belmont CA, US
Lori Sickels Friedman - San Carlos CA, US
Jian Huang - Millbrae CA, US

Assignee:

Genentech, Inc. - South San Francisco CA

International Classification:

A61K 31/553
A61K 31/519
A61K 31/565
A61K 31/4196
A61P 35/00

Abstract:

Provided are combination therapies comprising a PI3K inhibitor (e.g., inavolisib), a CDK4/6 inhibitor (e.g., palbociclib), and fulvestrant; and methods of treating hormone receptor positive and HER2 negative (HR+/HER2−) locally advanced or metastatic breast cancer in a patient (preferably a patient with a PIC3CA mutant patient) comprising administering a therapeutically effective amount of inavolisib, or a pharmaceutically acceptable salt thereof, a CDK4/6 inhibitor (e.g., palbociclib), and fulvestrant or letrozole.

US Patent:

20230069559, Mar 2, 2023

Filed:

Aug 31, 2021

Appl. No.:

17/462605

Inventors:

- Boise ID, US
Jian Huang - Union City CA, US
Tingjun Xie - Milpitas CA, US
Murong Lang - San Jose CA, US
Zhenming Zhou - San Jose CA, US

International Classification:

G06F 3/06

Abstract:

A request to perform a memory access operation on a plurality of memory cells of a memory device is receive. A request type associated with the memory access operation is determined. In response to determining that the request type associated with the request type associated with the memory access operation is a first request type, an error recovery operation associated with the first request type is performed. In response to determining that the request type associated with the memory access operation is a second request type, an error recovery operation associated with the second request type is performed.

US Patent:

20230027144, Jan 26, 2023

Filed:

Oct 3, 2022

Appl. No.:

17/958920

Inventors:

- Boise ID, US
Jian Huang - Union City CA, US
Jiangli Zhu - San Jose CA, US

International Classification:

G06F 11/10
G06F 11/14
G06F 11/07
G06F 3/06
G06F 11/30

Abstract:

An error associated with a read operation corresponding to a memory die of a memory subsystem is detected. In response to detecting the error, a first read throughput level of the memory subsystem is identified. A quantity of queues receiving operation requests is decreased, the decreased quantity of queues corresponding to a second read throughput level. A read retry operation associated with the memory die is initiated at the second read throughput level.

US Patent:

20170322968, Nov 9, 2017

Filed:

May 8, 2017

Appl. No.:

15/589759

Inventors:

- CUPERTINO CA, US
YUNKAI ZHOU - LOS ALTOS CA, US
JIAN HUANG - REDWOOD CITY CA, US
YUE KWEN JUSTIN YIP - SUNNYVALE CA, US

International Classification:

G06F 17/30
G06F 17/30
G06F 17/30

Abstract:

Systems and methods are disclosed for providing weighted evaluation. The system may comprise one or more processors and a memory storing instructions that, when executed by the one or more processors, cause the system to obtain a plurality of data point groups, obtain an inbound rank of each data point group based on one or more inbound ranks of one or more data groups linking to the data point group, obtain an outbound rank of the each data point group based on one or more outbound ranks of one or more data groups linked from the each data point group, obtain a group rank of the each data point group based on the inbound rank and the outbound rank of the each data point group, and process the data point groups according to the corresponding group ranks.

US Patent:

20170060695, Mar 2, 2017

Filed:

Aug 31, 2015

Appl. No.:

14/841154

Inventors:

- San Jose CA, US
Liana Sanoyan - Sunnyvale CA, US
Jian Huang - San Jose CA, US
Suresh Appavu - San Jose CA, US
Sandip Das - Sunnyvale CA, US
Paul Kazakov - San Jose CA, US
Prabhagaran Subramaniam - Chennai, IN
Mutharasan Nainar - Chennai, IN

International Classification:

G06F 11/14
G06F 17/30

Abstract:

A system and method for data replication for databases using an intermediary server, the intermediary server choosing the order in which databases are replicated, the utilities used for each of the steps in the data replication process, the timing of the replication, and/or the timing each step of the data replication process is performed.

US Patent:

20150058599, Feb 26, 2015

Filed:

Oct 31, 2014

Appl. No.:

14/529331

Inventors:

- Sunnyvale CA, US
Pradeep S. SINDHU - Los Altos Hills CA, US
Jeffrey G. LIBBY - Cupertino CA, US
Jian Hui HUANG - Fremont CA, US
Rajesh NAIR - Fremont CA, US
John KEEN - Mountain View CA, US

International Classification:

G06F 9/28
G06F 9/30

US Classification:

712 33, 712221

Abstract:

A processor may include a conditional arithmetic logic unit and a main arithmetic logic unit. The conditional arithmetic logic unit may perform a first arithmetic logic operation to generate a first result, and output the result. The main arithmetic logic unit may select input buses among a plurality of data buses that carry the first result from the conditional arithmetic logic unit, perform a second arithmetic logic operation on data provided by the selected input buses to generate a second result, and write the second result in a storage component.

Address:

2150 27 Ave, San Francisco, CA 94116

Phone:

(415)2726168

VIN:

WBAVC53597FZ75117

Make:

BMW

Model:

3 SERIES

Year:

2007